A system and method provide for monitoring and controlling fluid flow in semiconductor manufacturing apparatuses. The method and system include a vortex flow meter coupled to a digital readout that displays the measured flow rate and trip point. The flow meter display includes input devices used to adjust the trip point. The system and method provide for sending signals via a custom relay to the semiconductor manufacturing apparatus which is adapted to terminate a processing operation or change the fluid flow if the trip point is tripped. The system and method also provide for sending an electrical signal to a computer by way of a data acquisition unit and a converter. The converter converts the signal to a communication protocol consistent with the computer network and provides fluid flow information and trip point data as a function of time to the computer which then displays such data graphically.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
C23C 16/00 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
G01M 1/00 - Testing static or dynamic balance of machines or structures
2.
Solid state sensor for metal ion detection and trapping in solution
A device, apparatus and method for trapping metal ions and detecting metal ion contamination in a solution provide a semiconductor device formed on a semiconductor substrate and including an N-well formed over a P-type substrate and at least a contact portion of the N-well in electrical contact with the solution. When the semiconductor device is optically illuminated, a P/N junction is formed as a result of photovoltaic phenomena. Metal ions from the solution migrate to the contact area due to the voltage created at the P/N junction. The semiconductor device includes a conductive structure with conductive features separated by a gap and therefore in an initially electrically open state. When the ions migrate to the contact area, they precipitate, at least partially bridging the gap and creating conductance through the conductive structure. The conductance may be measured to determine the amount of metal ion contamination.
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
H01L 21/336 - Field-effect transistors with an insulated gate
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 27/11521 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
A method for forming a non-volatile memory cell is provided. The method comprises: forming a field region with a first impurity type in a semiconductor substrate, the field region having a first impurity concentration; forming a plurality of spaced apart higher concentration regions with the first impurity type within the field region, the higher concentration regions each having a higher concentration than the first impurity concentration; and forming a plurality of floating gate transistors in the field region between the higher concentration regions.
H01L 21/336 - Field-effect transistors with an insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 27/11521 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
A system and method provide for monitoring and controlling fluid flow in semiconductor manufacturing apparatuses. The method and system include a vortex flow meter coupled to a digital readout that displays the measured flow rate and trip point. The flow meter display includes input devices used to adjust the trip point. The system and method provide for sending signals via a custom relay to the semiconductor manufacturing apparatus which is adapted to terminate a processing operation or change the fluid flow if the trip point is tripped. The system and method also provide for sending an electrical signal to a computer by way of a data acquisition unit and a converter. The converter converts the signal to a communication protocol consistent with the computer network and provides fluid flow information and trip point data as a function of time to the computer which then displays such data graphically.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
C23C 16/00 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
G01M 1/00 - Testing static or dynamic balance of machines or structures
6.
Method and priority system for inventory management in semiconductor manufacturing
An inventory tracking system and method for use in semiconductor manufacturing provide for generating a priority score that determines the order in which lots of substrates should be run. The priority score is generated using an algorithm that takes into account external lot priority considerations, inventory factors in the manufacturing facility, and processing tool capability factors. The processing tool capability factors include factors related to tool status and tool restrictions and the inventory factors include factors related to line balance, WIP (work-in-progress) forecasts and various downstream considerations. The priority score is generated dynamically and displayed at each processing operation for each lot that is queued for processing at the indicated operation. Various algorithms are used and different weights are assigned to many factors in calculating numerical values for several factors that combine to produce the priority score. The generated priority score can be tool-specific or module-specific.
G06F 19/00 - Digital computing or data processing equipment or methods, specially adapted for specific applications (specially adapted for specific functions G06F 17/00;data processing systems or methods specially adapted for administrative, commercial, financial, managerial, supervisory or forecasting purposes G06Q;healthcare informatics G16H)
G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM]
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
A split gate flash cell device with floating gate transistors is provided. Each floating gate transistor is formed by providing a floating gate transistor substructure including an oxide disposed over a polysilicon gate disposed over a gate oxide disposed on a portion of a common source. Nitride spacers are formed along sidewalls of the floating gate transistor substructure and cover portions of the gate oxide that terminate at the sidewalls. An isotropic oxide etch is performed with the nitride spacers intact. The isotropic etch laterally recedes opposed edges of the oxide inwardly such that a width of the oxide is less than a width of the polysilicon gate. An inter-gate dielectric is formed over the floating gate transistor substructure and control gates are formed over the inter-gate dielectric to form the floating gate transistors.
Provided is a test pattern structure for determining overlay accuracy in a semiconductor device. The test pattern structure includes one or more resistor structures formed by patterning a lower silicon layer. Each includes a zigzag portion with leads at different spatial locations. An upper pattern is formed and includes at least one pattern feature formed over the resistor or resistors. The portions of the resistor or resistors not covered by the upper pattern feature will become silicided during a subsequent silicidation process. Resistance is measured to determine overlay accuracy as the resistor structures are configured such that the resistance of the resistor structure is determined by the degree of silicidation of the resistor structure which is determined by the overlay accuracy between the upper and lower patterns.
G01R 31/00 - Arrangements for testing electric propertiesArrangements for locating electric faultsArrangements for electrical testing characterised by what is being tested not provided for elsewhere
9.
Nonvolatile memory cell with improved isolation structures
An array of floating gate transistors of a non-volatile memory, NVM, cell includes floating gate transistors separated from one another by high-concentration dopant impurity regions and without using shallow trench isolation (STI) or field oxide (FOX) isolation structures. The array is formed over a substrate portion that includes a continuous and planar upper surface. The high-concentration dopant impurity regions are formed in a P-field region and are formed of the same dopant impurity species as the P-field region but of a higher concentration. The floating gate transistors are split-gate floating gate transistors in some embodiments.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/167 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form further characterised by the doping material
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
Multiple intertwined inductor coils combine to form one or more transformer devices of a semiconductor device. The intertwined inductor coils are formed of only two metallization layers and vias coupling the layers. The inductor coils are vertically oriented and include a magnetic axis parallel to the substrate surface. A plurality of metal wires are provided on both a first device level and a second device level. Each of the metal wires on the first device level is coupled to two wires on the second device level and forms a first inductor coil. The two metal wires on the second device level that form part of the first inductor coil, are separated by a third wire that is coupled to two different first device level metal wires and forms part of a different second inductor coil intertwined with the first inductor coil.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
11.
Statistical method for monitoring manufacturing equipment and processing operations
A statistical process control method for monitoring and controlling semiconductor manufacturing processing operations is provided. For a chosen processing operation, multiple measurement sites are used to generate data of a measurable characteristic that is impacted by and associated with the processing operation. The data from the sites is compared over time and one or more outlier sites are identified. The outlier sites are the sites at which the data values are most divergent from the rest of the data. Algorithms are used to mathematically compare the outlier sites to the other sites to produce a comparative index. The comparative index is monitored graphically or otherwise to identify changes in the processing operation, and corrective actions are taken.
H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid-state devices, or of parts thereof
G01R 31/26 - Testing of individual semiconductor devices
H01L 21/302 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
H01L 21/461 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layersAfter-treatment of these layers
G05B 19/4065 - Monitoring tool breakage, life or condition
12.
Floating gate flash cell with extended floating gate
Provided is a floating gate flash cell and method for forming the same. The flash includes two floating gate transistors and a common source area therebetween. Each floating gate transistor includes a floating gate having a central portion disposed over a substrate surface and opposed lateral edges that extend into trenches and below the substrate surface. A control gate is disposed over said floating gate with a control gate dielectric between the floating gate and the control gate. The floating gates have side edges that are orthogonal to the opposed lateral edges and a common source area which is a substrate diffusion area, is positioned between respective facing side edges of the floating gates.
MIM capacitors that are temperature and/or voltage independent, and a methodology for formulating the MIM capacitors for use in semiconductor integrated circuits, is provided. Vertical MIM capacitive structures include at least two vertically separated electrodes and a capacitor dielectric that includes portions of different dielectric materials provided in a desired area ratio. The disclosure provided for selecting dielectrics and dielectric thicknesses, determining an area ratio that produces temperature and/or voltage independent MIM capacitors, and forming capacitive devices with the desired area ratio. In one embodiment, the capacitor dielectric includes at least one SiO dielectric portion and at least one SiN dielectric portion and a total capacitive area includes the SiN and SiO dielectric portions arranged such that the ratio of the area of the SiO portions to the area of the SiN portions is about 1.15:1.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 27/08 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
A device, apparatus and method for trapping metal ions and detecting metal ion contamination in a solution provide a semiconductor device formed on a semiconductor substrate and including an N-well formed over a P-type substrate and at least a contact portion of the N-well in electrical contact with the solution. When the semiconductor device is optically illuminated, a P/N junction is formed as a result of photovoltaic phenomena. Metal ions from the solution migrate to the contact area due to the voltage created at the P/N junction. The semiconductor device includes a conductive structure with conductive features separated by a gap and therefore in an initially electrically open state. When the ions migrate to the contact area, they precipitate, at least partially bridging the gap and creating conductance through the conductive structure. The conductance may be measured to determine the amount of metal ion contamination.
A statistical process control method for monitoring and controlling semiconductor manufacturing processing operations is provided. For a chosen processing operation, multiple measurement sites are used to generate data of a measurable characteristic that is impacted by and associated with the processing operation. The data from the sites is compared over time and one or more outlier sites are identified. The outlier sites are the sites at which the data values are most divergent from the rest of the data. Algorithms are used to mathematically compare the outlier sites to the other sites to produce a comparative index. The comparative index is monitored graphically or otherwise to identify changes in the processing operation, and corrective actions are taken.
H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid-state devices, or of parts thereof
G01R 31/26 - Testing of individual semiconductor devices
H01L 21/302 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
H01L 21/461 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layersAfter-treatment of these layers
A split gate flash cell device with floating gate transistors is provided. Each floating gate transistor is formed by providing a floating gate transistor substructure including an oxide disposed over a polysilicon gate disposed over a gate oxide disposed on a portion of a common source. Nitride spacers are formed along sidewalls of the floating gate transistor substructure and cover portions of the gate oxide that terminate at the sidewalls. An isotropic oxide etch is performed with the nitride spacers intact. The isotropic etch laterally recedes opposed edges of the oxide inwardly such that a width of the oxide is less than a width of the polysilicon gate. An inter-gate dielectric is formed over the floating gate transistor substructure and control gates are formed over the inter-gate dielectric to form the floating gate transistors.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
17.
Method for using acoustic waves for purging filters in semiconductor manufacturing equipment
An apparatus and method for qualifying a filter used to filter fluid used in a coating operation associated with photolithography or other semiconductor manufacturing processes, provides a semiconductor manufacturing tool that includes a filter and an acoustic wave generator. The filter may be housed inside a filter housing and the acoustic wave generator may produce ultrasonic, megasonic or other acoustic energy. The acoustic wave generator contacts or is in close proximity with the filter housing and provides acoustic wave energy to the filter through the housing. The acoustic wave energy causes any bubbles in the filter to become disengaged.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
18.
Silicided MOS capacitor explosive device initiator
An explosive device using a semiconductor explosion initiator device provides an MOS capacitor formed on a semiconductor substrate and including a silicide layer formed over a doped silicon layer formed over an oxide layer. The oxide layer is formed on an N-well formed in a semiconductor substrate. A voltage source applies a voltage which may be a pulsed voltage, across the MOS capacitor sufficient to cause the avalanche breakdown of the oxide layer and the diffusion of metal from the silicide layer into the doped silicon of the N-well formed in the substrate. The chemical reaction between the metal and the doped silicon causes the generation of a plasma which ignites a pyrotechnic material or ignites or detonates other explosive material in contact with the semiconductor explosion initiator device.
A solar cell with an absorber layer including three dimensional tubular projections and the method for forming the same, is provided. The three dimensional tubular projections are formed in various configurations and include surfaces facing in various directions and are adapted to absorb sunlight directed to the solar cell panel at various angles. The method for forming the absorber layer includes introducing impurities onto a layer over a solar cell substrate to form as nucleation sites and depositing an absorber layer to form a base layer portion and tubular projections at the nucleation sites. The solar cell is exposed to sunlight and the absorber layer including the three dimensional tubular projections, absorbs direct and reflected sunlight directed to the solar cell at various angles.
H01L 31/0352 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
H01L 31/068 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
20.
Threaded dispense nozzle and alignment method and device for photoresist and other fluid coaters
Provided is a fluid dispensing system with a dispense nozzle with a threaded outer surface and a fluid dispensing apparatus with a movable dispenser arm with an opening that includes threaded inner walls that receive the dispense nozzle therein. Also provided is a method for aligning a dispense head in a coating tool. Horizontal alignment is achieved by rotating the dispense nozzle until its tip is in contact with the chuck then laterally adjusting the dispenser arm position so that the tip is positioned over a center of the chuck. Vertical alignment is achieved by rotating the dispense nozzle until an indicia of the dispense nozzle is at the same vertical location as a designated physical feature of the dispenser arm.
B05D 3/12 - Pretreatment of surfaces to which liquids or other fluent materials are to be appliedAfter-treatment of applied coatings, e.g. intermediate treating of an applied coating preparatory to subsequent applications of liquids or other fluent materials by mechanical means
B05B 1/00 - Nozzles, spray heads or other outlets, with or without auxiliary devices such as valves, heating means
B05B 15/08 - Means for adjusting position of spray heads
B05B 13/02 - Means for supporting workArrangement or mounting of spray headsAdaptation or arrangement of means for feeding work
B05B 15/06 - Mountings, supporting or holding means, or rests for spray heads or other outlets when in use or out of use (B05B 15/10 takes precedence)
B05D 1/00 - Processes for applying liquids or other fluent materials
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
B05B 13/04 - Means for supporting workArrangement or mounting of spray headsAdaptation or arrangement of means for feeding work the spray heads being moved during operation
21.
Plasma pre-treatment for improved uniformity in semiconductor manufacturing
Methods for forming a semiconductor devices are provided. A plasma pre-treatment operation is performed on a photoresist pattern formed over a material disposed over a substrate, and reduces critical dimensions (CDs) of features of the photoresist pattern to a greater extent at a central portion of the substrate than at outer portions of the substrate, thereby forming a treated pattern with a gradient of CDs. The material is then etched using the treated pattern as a photomask. An overetch operation that tends to reduce CDs of the etched features of the material to a greater extent at outer portions of the substrate than at the central portion of the substrate, is employed. The plasma pre-treatment operation is designed in conjunction with the overetch characteristics and, in combination, the operations produce etched features having CDs with a high degree of uniformity across the substrate.
A one-time programmable (OTP) memory cell includes a dual date transistor and, in some embodiments, two transistors. The dual gate transistor is formed using the same processing operations used to form floating gate transistors in other areas of the semiconductor device. The dual gate transistor includes an upper gate isolated from a floating gate by a floating gate oxide, the combination of which produces an anti-fuse. The nonvolatile memory device may include a plurality of such OTP memory cells and one or more OTP memory cells are selected and programmed by applying a voltage sufficient to blow the anti-fuse by causing the floating gate oxide layer to break down and the upper gate to become shorted to the floating gate.
G11C 17/16 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
23.
Split gate flash cell and method for making the same
A split gate flash cell device with floating gate transistors is provided. Each floating gate transistor is formed by providing a floating gate transistor substructure including an oxide disposed over a polysilicon gate disposed over a gate oxide disposed on a portion of a common source. Nitride spacers are formed along sidewalls of the floating gate transistor substructure and cover portions of the gate oxide that terminate at the sidewalls. An isotropic oxide etch is performed with the nitride spacers intact. The isotropic etch laterally recedes opposed edges of the oxide inwardly such that a width of the oxide is less than a width of the polysilicon gate. An inter-gate dielectric is formed over the floating gate transistor substructure and control gates are formed over the inter-gate dielectric to form the floating gate transistors.
H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
A shallow trench isolation (STI) structure includes a top surface formed completely of silicon nitride. The top surface of the STI structure is coplanar with a top substrate surface or extends above the top substrate surface. The STI structures include further dielectric materials beneath the silicon nitride and an oxide liner and any portions that extend above the substrate surface are formed of silicon nitride.
H01L 21/70 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereofManufacture of integrated circuit devices or of specific parts thereof
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
A recipe management system associates a selected process recipe with a recipe group and checks to see if other recipes of the recipe group have been updated since the selected recipe was last run. If another recipe of the recipe group has been run and adjustments have been made to the other recipe based on an analysis of a manufacturing or test run, the recipe management system identifies the selected recipe as requiring an update. The recipe management system sends error reports noting the discrepancy between a parameter setting changed in the test run and needing adjustment in the selected run. The recipe management system also effectuates the needed adjustments to the selected recipe before the selected recipe is allowed to be used in the manufacturing environment.
G06F 19/00 - Digital computing or data processing equipment or methods, specially adapted for specific applications (specially adapted for specific functions G06F 17/00;data processing systems or methods specially adapted for administrative, commercial, financial, managerial, supervisory or forecasting purposes G06Q;healthcare informatics G16H)
G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM]
26.
Semiconductor device with one-time programmable memory cell including anti-fuse with metal/polycide gate
A one-time programmable (OTP) memory cell includes two transistors including a dual gate transistor. The dual gate transistor is formed using the same processing operations used to form floating gate transistors in other areas of the semiconductor device. The dual gate transistor includes an upper gate isolated from a floating gate by a floating gate oxide, the combination of which produces an anti-fuse. The nonvolatile memory device may include a plurality of such OTP memory cells and one or more OTP memory cells are selected and programmed by applying a voltage sufficient to blow the anti-fuse by causing the floating gate oxide layer to break down and the upper gate to become shorted to the floating gate.
A vertically integrated semiconductor device includes multiple continuous single crystal silicon layers vertically separated from one another by a dielectric layer or layers. Semiconductor devices are disposed on an underlying single crystal silicon substrate and the continuous single crystal silicon layers. The individual devices are interconnected to one another using tungsten or doped polysilicon leads that extend through openings formed in the continuous single crystal silicon layers. The method for forming the structure includes forming a dielectric material over the single crystal silicon layer or substrate and forming an opening extending down to the surface of the single crystal silicon material to act as a seed layer. An epitaxial silicon growth process begins at the seed location and laterally overgrows the openings. Growth fronts from the various seed locations meet to form a continuous single crystal silicon layer which is then polished.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 27/085 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
28.
Floating gate flash cell device and method for partially etching silicon gate to form the same
A method for forming a split gate flash cell memory device provides for establishing a floating gate region then using spacers or other hard mask materials that cover opposed edges of a gate electrode material in the gate region, to serve as hard masks during an etching operation that partially etches the gate electrode material which may be polysilicon. The gate electrode so produced serves as a floating gate electrode and includes a recessed central portion flanked by a pair of opposed upwardly extending fins which may terminate upwardly at an apex. A floating gate oxide is then formed by thermal oxidation and/or oxide deposition techniques.
A one-time programmable (OTP) memory cell includes two transistors including a dual gate transistor. The dual gate transistor is formed using the same processing operations used to form floating gate transistors in other areas of the semiconductor device. The dual gate transistor includes an upper gate isolated from a floating gate by a floating gate oxide, the combination of which produces an anti-fuse. The nonvolatile memory device may include a plurality of such OTP memory cells and one or more OTP memory cells are selected and programmed by applying a voltage sufficient to blow the anti-fuse by causing the floating gate oxide layer to break down and the upper gate to become shorted to the floating gate.
A shallow trench isolation (STI) structure and methods for forming the same provide an STI structure with a top surface formed completely of silicon nitride. The methods for forming the STI structures provide for at least one nitride deposition step followed by a further nitride deposition step to re-fill divots that occur along the upper portions of the trench sidewalls.
Provided is a test pattern structure for determining overlay accuracy in a semiconductor device. The test pattern structure includes one or more resistor structures formed by patterning a lower silicon layer. Each includes a zigzag portion with leads at different spatial locations. An upper pattern is formed and includes at least one pattern feature formed over the resistor or resistors. The portions of the resistor or resistors not covered by the upper pattern feature will become silicided during a subsequent silicidation process. Resistance is measured to determine overlay accuracy as the resistor structures are configured such that the resistance of the resistor structure is determined by the degree of silicidation of the resistor structure which is determined by the overlay accuracy between the upper and lower patterns.
Method of fabricating vertical integrated semiconductor device with multiple continuous single crystal silicon layers vertically separated from one another
A vertically integrated semiconductor device includes multiple continuous single crystal silicon layers vertically separated from one another by a dielectric layer or layers. Semiconductor devices are disposed on an underlying single crystal silicon substrate and the continuous single crystal silicon layers. The individual devices are interconnected to one another using tungsten or doped polysilicon leads that extend through openings formed in the continuous single crystal silicon layers. The method for forming the structure includes forming a dielectric material over the single crystal silicon layer or substrate and forming an opening extending down to the surface of the single crystal silicon material to act as a seed layer. An epitaxial silicon growth process begins at the seed location and laterally overgrows the openings. Growth fronts from the various seed locations meet to form a continuous single crystal silicon layer which is then polished.
An apparatus and method for qualifying a filter used to filter fluid used in a coating operation associated with photolithography or other semiconductor manufacturing processes, provides a semiconductor manufacturing tool that includes a filter and an acoustic wave generator. The filter may be housed inside a filter housing and the acoustic wave generator may produce ultrasonic, megasonic or other acoustic energy. The acoustic wave generator contacts or is in close proximity with the filter housing and provides acoustic wave energy to the filter through the housing. The acoustic wave energy causes any bubbles in the filter to become disengaged.
B05C 11/00 - Component parts, details or accessories not specifically provided for in groups
B01D 29/72 - Regenerating the filter material in the filter by forces created by movement of the filter element involving vibrations
B08B 9/00 - Cleaning hollow articles by methods or apparatus specially adapted thereto
B01D 27/00 - Cartridge filters of the throw-away type
B01D 33/00 - Filters with filtering elements which move during the filtering operation
B01D 33/17 - Filters with filtering elements which move during the filtering operation with rotary plane filtering surfaces with rotary filtering tables
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
34.
Defect free deep trench method for semiconductor chip
A method for forming large substantially defect-free void areas on a semiconductor integrated circuit chip includes processing the chip through the passivation level processing operations then forming one or more openings in a designated blank area of the integrated circuit chip in a separate dedicated etching operation. The one or more openings may constitute 5-10% or more of the total area of the semiconductor chip. The void areas are deep trench openings that extend through the passivation layer and through all of the other material layers in the blank area exposing the substrate surface in one embodiment and through all material layers except for a field oxide layer formed directly on the substrate in another embodiment.
Methods for forming floating gate transistors provide for using a self-aligned plug formed over a floating gate electrode without use of an additional photolithography operation. The plug is centrally disposed and is formed and aligned using spacers. The spacers are formed alongside edges of a patterned sacrificial, oxidation resistant layer that includes an opening that defines the floating gate region. The plug may be formed of a silicon material and which becomes oxidized along with the floating gate such that the plug eventually forms part of the floating gate electrode or the plug may be formed of a nitride or other oxidation resistant material to retard or prevent oxidation in the central portion of the floating gate in which the plug is aligned.
Methods for forming split gate flash cell structures provide for symmetrical cells that are immune to misalignment of the photoresist pattern when forming the control gates. Spacers are utilized to form the floating gates in the floating gate transistors used in the flash cells. The spacers may be oxide spacers used to mask a polysilicon layer that will form the floating gates or the spacers may be polysilicon spacers that will themselves form the floating gates. The inter-gate oxide of the floating gate transistors may be formed using HTO or may be deposited. Hard mask spacers are used in conjunction with the control gate photoresist patterning operation to control the size and configuration of the control gate and the channel length.
A method for forming a split gate flash cell memory device provides for establishing a floating gate region then using spacers or other hard mask materials that cover opposed edges of a gate electrode material in the gate region, to serve as hard masks during an etching operation that partially etches the gate electrode material which may be polysilicon. The gate electrode so produced serves as a floating gate electrode and includes a recessed central portion flanked by a pair of opposed upwardly extending fins which may terminate upwardly at an apex. A floating gate oxide is then formed by thermal oxidation and/or oxide deposition techniques.
H01L 21/336 - Field-effect transistors with an insulated gate
H01L 21/283 - Deposition of conductive or insulating materials for electrodes
H01L 21/31 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layersSelection of materials for these layers
38.
Methods and structures for customized STI structures in semiconductor devices
A method and structure provide for customizing STI, shallow trench isolation, structures in various parts of a system-on-chip, SOC, or other semiconductor integrated circuit device. Within an individual chip, STI structures are formed to include different dielectric thicknesses that are particularly advantageous for the particular device portion of the SOC chip in which the STI structure is formed.
A method for forming a split gate flash cell device provides for forming floating gate transistors. Each floating gate transistor is formed by providing a floating gate transistor substructure including an oxide disposed over a polysilicon gate disposed over a gate oxide disposed on a portion of a common source. Nitride spacers are formed along sidewalls of the floating gate transistor substructure and cover portions of the gate oxide that terminate at the sidewalls. An isotropic oxide etch is performed with the nitride spacers intact. The isotropic etch laterally recedes opposed edges of the oxide inwardly such that a width of the oxide is less than a width of the polysilicon gate. An inter-gate dielectric is formed over the floating gate transistor substructure and control gates are formed over the inter-gate dielectric to form the floating gate transistors.
An explosive device using a semiconductor explosion initiator device provides an MOS capacitor formed on a semiconductor substrate and including a silicide layer formed over a doped silicon layer formed over an oxide layer. The oxide layer is formed on an N-well formed in a semiconductor substrate. A voltage source applies a voltage which may be a pulsed voltage, across the MOS capacitor sufficient to cause the avalanche breakdown of the oxide layer and the diffusion of metal from the silicide layer into the doped silicon of the N-well formed in the substrate. The chemical reaction between the metal and the doped silicon causes the generation of a plasma which ignites a pyrotechnic material or ignites or detonates other explosive material in contact with the semiconductor explosion initiator device.
A device, apparatus and method for trapping metal ions and detecting metal ion contamination in a solution provide a semiconductor device formed on a semiconductor substrate and including an N-well formed over a P-type substrate and at least a contact portion of the N-well in electrical contact with the solution. When the semiconductor device is optically illuminated, a P/N junction is formed as a result of photovoltaic phenomena. Metal ions from the solution migrate to the contact area due to the voltage created at the P/N junction. The semiconductor device includes a conductive structure with conductive features separated by a gap and therefore in an initially electrically open state. When the ions migrate to the contact area, they precipitate, at least partially bridging the gap and creating conductance through the conductive structure. The conductance may be measured to determine the amount of metal ion contamination.
A ball bearing having external surfaces coated with ceramic materials is provided. The raceways of the ball bearing may advantageously be formed of metal such as stainless steel. The ceramic coating acts as an insulator increasing the resistance of the ball bearing to heat within the ball bearing environment. The balls within the raceway of the ball bearing may advantageously be coated with a lubricant to decrease friction in the ball bearing because the insulating ceramic coating prevents the environmental heat from causing the degradation of the lubricant.
An optical lithography exposure apparatus which may be a stepper or a scanner, provides a wafer chuck that retains a wafer and at least one opaque exposure shield that extends over a discrete peripheral edge portion of the wafer thereby preventing illumination from exposing the portion of the wafer beneath the exposure shield. In a positive photoresist system, the portions of the wafer blocked from exposure by the shields, include alignment marks and the unexposed photoresist remains over the alignment marks thereby protecting the alignment marks from destruction or damage during subsequent patterning operations used to form patterns in the film being patterned.
A method and a computer readable medium includes instructions for obtaining time data as programmed into processing recipes or as recorded when a wafer is processed and transferred during lithography operations. The data is parsed and saved into an MES database. A report server accesses the database responsive to a query made of the database. A query may specify one or more fabrication parameters. The specified fabrication parameter or parameters is fixed and a data display is provided that compares times for processing and transferring wafers in various lithography operations used in the production of the semiconductor device and bottlenecks in lithography operations are identified by the comparative data.
G06F 19/00 - Digital computing or data processing equipment or methods, specially adapted for specific applications (specially adapted for specific functions G06F 17/00;data processing systems or methods specially adapted for administrative, commercial, financial, managerial, supervisory or forecasting purposes G06Q;healthcare informatics G16H)
45.
Method and apparatus for cleaning semiconductor photolithography tools
A system for cleaning semiconductor lithography tools provides for cycling a polished-side down semiconductor wafer through the lithography tool using conventional automated robotics for loading and unloading the wafer from a vacuum chuck of the lithography tool. The vacuum chuck may provide a continuous clamping vacuum feature and may include a vacuum ring that surround the periphery of the vacuum chuck. The chuck and vacuum ring may advantageously be formed of a high accuracy ceramic or plastic such as ZeroDur ceramic. The polished side of the semiconductor wafer includes grooves in a polished surface and which extend inwardly from a peripheral edge of the wafer, the grooves provide gaps between the wafer and chuck allowing the wafer to be released by a slow loss of vacuum-pressure through the gaps. The pristine clean polished surface of the wafer getters contaminating particles from the chuck.
A method, system and encoded computer instructions provide for automatic generation of a metrology recipe without referencing a wafer. The highly accurate metrology recipe provides for locating measurement locations corresponding to test features on the wafer and directing the metrology tool to the locations, by calculating coordinates for the measurement locations based on mask data, lithography tool data, CAD data and process data. The metrology recipe directs the metrology tool to within 10 microns of test features formed on the wafer. Criteria may be input to a data base to identify multiple existing recipes and the automatically generated recipe may be generated to replace each identified recipe.
