Systems and methods described herein involve executing, using an artificial intelligence System on Chip (AI SoC), a machine learning model on received televised content, the machine learning model configured to identify objects displayed on the received televised content; displaying, through a mobile application interface, the identified objects for selection; and for a selection of one or more objects from the identified objects and an overlay through the mobile application interface, modifying a display of the received televised content to display the overlay.
H04N 21/466 - Learning process for intelligent management, e.g. learning user preferences for recommending movies
H04N 21/4725 - End-user interface for requesting content, additional data or servicesEnd-user interface for interacting with content, e.g. for content reservation or setting reminders, for requesting event notification or for manipulating displayed content for requesting additional data associated with the content using interactive regions of the image, e.g. hot spots
H04N 21/475 - End-user interface for inputting end-user data, e.g. PIN [Personal Identification Number] or preference data
H04N 21/4788 - Supplemental services, e.g. displaying phone caller identification or shopping application communicating with other users, e.g. chatting
2.
CONTINUOUS ADAPTIVE DATA CAPTURE OPTIMIZATION FOR INTERFACE CIRCUITS
A method for operating a data interface circuit whereby calibration adjustments for data bit capture are made without disturbing normal system operation includes initially establishing, using a first calibration method where a data bit pattern received by the data interface circuit is predictable, an optimal sampling point for sampling data bits received by the data interface circuit, and during a normal system operation and without disturbing the normal system operation, performing a second calibration method where the data bit pattern received by the data interface circuit is unpredictable. The second calibration method determines an amount of a timing drift for received data bit edge transitions and adjusts the optimal timing point determined by the first calibration method to create a revised optimal timing point. The second calibration method samples fringe timing points associated with the transition edges of a data bit.
G06F 13/362 - Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
G11C 8/18 - Address timing or clocking circuitsAddress control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass
H03K 5/133 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active-delay devices
H03K 5/14 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of delay lines
A computer-implemented method includes an act of configuring hardware to cause at least a part of the hardware to operate as a double data rate (DDR) memory controller, and to produce a capture clock to time a read data path, where a timing of the capture clock is based on a first clock signal of a first clock, delay the first clock signal to produce a delayed first clock signal, adjust the delay such that at least one clock edge of the delayed first clock signal is placed nearer to at least one clock edge of at least one data strobe (DQS), or at least one signal dependent on a DQS timing, and produce a modified timing of the capture clock based on the delay of the first clock signal.
G06F 1/04 - Generating or distributing clock signals or signals derived directly therefrom
G06F 1/08 - Clock generators with changeable or programmable clock frequency
G06F 1/12 - Synchronisation of different clock signals
G06F 1/14 - Time supervision arrangements, e.g. real time clock
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
G11C 7/04 - Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 7/22 - Read-write [R-W] timing or clocking circuitsRead-write [R-W] control signal generators or management
G11C 11/40 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors
G11C 11/4093 - Input/output [I/O] data interface arrangements, e.g. data buffers
G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
4.
SYSTEMS AND METHODS INVOLVING ARTIFICIAL INTELLIGENCE AND CLOUD TECHNOLOGY FOR SERVER SOC
Example implementations described herein are directed to systems and methods for a server hub device that is configured to execute artificial intelligence/neural network models through processing input data and generating metadata or instructions to edge devices. In example implementations, the AI/NN operations are conducted through executing logical shifts (e.g., by shifter circuits) on log-quantized parameters corresponding to such operations.
H04N 21/431 - Generation of visual interfacesContent or additional data rendering
G06F 15/78 - Architectures of general purpose stored program computers comprising a single central processing unit
G06F 16/583 - Retrieval characterised by using metadata, e.g. metadata not derived from the content or metadata generated manually using metadata automatically derived from the content
5.
IMPLEMENTATIONS AND METHODS FOR PROCESSING NEURAL NETWORK IN SEMICONDUCTOR HARDWARE
Aspects of the present disclosure involve systems, methods, computer instructions, and artificial intelligence processing elements (AIPEs) involving a shifter circuit or equivalent circuitry/hardware/computer instructions thereof configured to intake shiftable input derived from input data for a neural network operation; intake a shift instruction derived from a corresponding log quantized parameter of a neural network or a constant value; and shift the shiftable input in a left direction or a right direction according to the shift instruction to form shifted output representative of a multiplication of the input data with the corresponding log quantized parameter of the neural network.
Aspects of the present disclosure involve systems, methods, computer instructions, and an edge system involving a memory configured to store an object detection/classification model in a form of a trained neural network represented by one or more log quantized parameter values, the object detection/classification model configured to classify one or more objects on image data through one or more neural network operations according to the log quantized parameter values of the trained neural network; and a system on chip (SoC) or equivalent circuitry/hardware/computer instructions thereof configured to intake the image data; execute one or more trained neural network models through the one or more neural network operations in connection with the image data; add one or more overlays to the image data based on the classified one or more objects from the image data; and provide the image data with the added overlays as output.
H04N 21/462 - Content or additional data management e.g. creating a master electronic program guide from data received from the Internet and a Head-end or controlling the complexity of a video stream by scaling the resolution or bit-rate based on the client capabilities
H04N 21/232 - Content retrieval operation within server, e.g. reading video streams from disk arrays
H04N 21/435 - Processing of additional data, e.g. decrypting of additional data or reconstructing software from modules extracted from the transport stream
H04N 21/44 - Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
H04N 21/466 - Learning process for intelligent management, e.g. learning user preferences for recommending movies
A computer-implemented method includes an act of configuring hardware to cause at least a part of the hardware to operate as a double data rate (DDR) memory controller, and to produce a capture clock to time a read data path, where a timing of the capture clock is based on a first clock signal of a first clock, delay the first clock signal to produce a delayed first clock signal, adjust the delay such that at least one clock edge of the delayed first clock signal is placed nearer to at least one clock edge of at least one data strobe (DQS), or at least one signal dependent on a DQS timing, and produce a modified timing of the capture clock based on the delay of the first clock signal.
G06F 1/04 - Generating or distributing clock signals or signals derived directly therefrom
G06F 1/08 - Clock generators with changeable or programmable clock frequency
G06F 1/12 - Synchronisation of different clock signals
G06F 1/14 - Time supervision arrangements, e.g. real time clock
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 7/22 - Read-write [R-W] timing or clocking circuitsRead-write [R-W] control signal generators or management
G11C 11/4093 - Input/output [I/O] data interface arrangements, e.g. data buffers
G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
G11C 7/04 - Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
G11C 11/40 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors
8.
Continuous adaptive data capture optimization for interface circuits
A method for operating a data interface circuit whereby calibration adjustments for data bit capture are made without disturbing normal system operation includes initially establishing, using a first calibration method where a data bit pattern received by the data interface circuit is predictable, an optimal sampling point for sampling data bits received by the data interface circuit, and during a normal system operation and without disturbing the normal system operation, performing a second calibration method where the data bit pattern received by the data interface circuit is unpredictable. The second calibration method determines an amount of a timing drift for received data bit edge transitions and adjusts the optimal timing point determined by the first calibration method to create a revised optimal timing point. The second calibration method samples fringe timing points associated with the transition edges of a data bit.
H03K 5/14 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of delay lines
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 13/362 - Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
G11C 8/18 - Address timing or clocking circuitsAddress control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
H03K 5/133 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active-delay devices
Systems and methods for automatically gating a data strobe during a read operation by the DRAM are disclosed. The method includes detecting, and automatically opening the gate when the DQS signal is driven. A system for automatically gating a Data Strobe (DQS) is disclosed which, on detection at an Input-Output (IO) receiver of a host chip, gates, at the host chip, the DQS signal based on the detection such that the gate is opened when the DQS signal is driven. A host chip and an input output receiver of the host chip are also disclosed.
Systems and methods described herein involve executing, using an artificial intelligence System on Chip (AI SoC), a machine learning model on received televised content, the machine learning model configured to identify objects displayed on the received televised content; displaying, through a mobile application interface, the identified objects for selection; and for a selection of one or more objects from the identified objects and an overlay through the mobile application interface, modifying a display of the received televised content to display the overlay.
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
Aspects of the present disclosure involve systems, methods, computer instructions, and artificial intelligence processing elements (AIPEs) involving a shifter circuit or equivalent circuitry/hardware/computer instructions thereof configured to intake shiftable input derived from input data for a neural network operation; intake a shift instruction derived from a corresponding log quantized parameter of a neural network or a constant value; and shift the shiftable input in a left direction or a right direction according to the shift instruction to form shifted output representative of a multiplication of the input data with the corresponding log quantized parameter of the neural network.
G06F 5/01 - Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
Aspects of the present disclosure involve systems, methods, computer instructions, and an edge system involving a memory configured to store an object detection/classification model in a form of a trained neural network represented by one or more log quantized parameter values, the object detection/classification model configured to classify one or more objects on image data through one or more neural network operations according to the log quantized parameter values of the trained neural network; and a system on chip (SoC) or equivalent circuitry/hardware/computer instructions thereof configured to intake the image data; execute one or more trained neural network models through the one or more neural network operations in connection with the image data; add one or more overlays to the image data based on the classified one or more objects from the image data; and provide the image data with the added overlays as output.
Example implementations described herein are directed to systems and methods for a server hub device that is configured to execute artificial intelligence/neural network models through processing input data and generating metadata or instructions to edge devices. In example implementations, the AI/NN operations are conducted through executing logical shifts (e.g., by shifter circuits) on log-quantized parameters corresponding to such operations.
Aspects of the present disclosure involve systems, methods, computer instructions, and an edge system involving a memory configured to store an object detection/classification model in a form of a trained neural network represented by one or more log quantized parameter values, the object detection/classification model configured to classify one or more objects on image data through one or more neural network operations according to the log quantized parameter values of the trained neural network; and a system on chip (SoC) or equivalent circuitry/hardware/computer instructions thereof configured to intake the image data; execute one or more trained neural network models through the one or more neural network operations in connection with the image data; add one or more overlays to the image data based on the classified one or more objects from the image data; and provide the image data with the added overlays as output.
A computer-implemented method includes an act of configuring hardware to cause at least a part of the hardware to operate as a double data rate (DDR) memory controller, and to produce a capture clock to time a read data path, where a timing of the capture clock is based on a first clock signal of a first clock, delay the first clock signal to produce a delayed first clock signal, adjust the delay such that at least one clock edge of the delayed first clock signal is placed nearer to at least one clock edge of at least one data strobe (DQS), or at least one signal dependent on a DQS timing, and produce a modified timing of the capture clock based on the delay of the first clock signal.
G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 7/22 - Read-write [R-W] timing or clocking circuitsRead-write [R-W] control signal generators or management
G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G06F 1/04 - Generating or distributing clock signals or signals derived directly therefrom
G06F 1/08 - Clock generators with changeable or programmable clock frequency
G06F 1/12 - Synchronisation of different clock signals
G06F 1/14 - Time supervision arrangements, e.g. real time clock
G11C 11/4093 - Input/output [I/O] data interface arrangements, e.g. data buffers
G11C 7/04 - Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
G11C 11/40 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors
16.
Continuous adaptive data capture optimization for interface circuits
A method for operating a data interface circuit whereby calibration adjustments for data bit capture are made without disturbing normal system operation includes initially establishing, using a first calibration method where a data bit pattern received by the data interface circuit is predictable, an optimal sampling point for sampling data bits received by the data interface circuit, and during a normal system operation and without disturbing the normal system operation, performing a second calibration method where the data bit pattern received by the data interface circuit is unpredictable. The second calibration method determines an amount of a timing drift for received data bit edge transitions and adjusts the optimal timing point determined by the first calibration method to create a revised optimal timing point. The second calibration method samples fringe timing points associated with the transition edges of a data bit.
G11C 8/18 - Address timing or clocking circuitsAddress control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
H03K 5/133 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active-delay devices
H03K 5/14 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of delay lines
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass
17.
Continuous adaptive data capture optimization for interface circuits
A data interface circuit wherein calibration adjustments for data bit capture are made without disturbing normal system operation, is described. A plurality of DLL capture and delay circuits for sampling a trained optimal sampling point as well as leading and trailing sampling points are defined. A first stream of data bits is input to the data interface circuit and using a first calibration method, a first optimal sampling point for sampling the data bits input is established. A second stream of data bits is input to the data interface circuit during normal system operation. A second calibration method is performed that is different from the first, the second calibration method being performed whereby: at least one reference data path is established for sampling transition edges of the second stream of data bits input to the data interface during normal system operation.
G11C 8/18 - Address timing or clocking circuitsAddress control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
H03K 5/133 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active-delay devices
H03K 5/14 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of delay lines
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass
18.
Double data rate (DDR) memory controller apparatus and method
In accordance with one embodiment, a computer-implemented method is provided, comprising the act of: configuring code or hardware to cause at least part of the hardware to operate as a double data rate (DDR) memory controller and to: produce a capture clock to time a read data path, where a timing of the capture clock is based on a first clock signal of a first clock, delay the first clock signal to produce a delayed first clock signal, adjust the delay such that at least one clock edge of the delayed first clock signal is placed nearer to at least one clock edge of: at least one data strobe (DQS), or at least one signal dependent on a DQS timing, and produce a modified timing of the capture clock based on the delay of the first clock signal.
G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 7/22 - Read-write [R-W] timing or clocking circuitsRead-write [R-W] control signal generators or management
G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G06F 1/04 - Generating or distributing clock signals or signals derived directly therefrom
G06F 1/08 - Clock generators with changeable or programmable clock frequency
G06F 1/12 - Synchronisation of different clock signals
G06F 1/14 - Time supervision arrangements, e.g. real time clock
G11C 11/4093 - Input/output [I/O] data interface arrangements, e.g. data buffers
G11C 7/04 - Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
G11C 11/40 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors
19.
Double data rate (DDR) memory controller apparatus and method
In accordance with one embodiment, a computer-implemented method is provided, comprising: configuring code to cause at least part of hardware to operate as a double data rate (DDR) memory controller and to produce one or more capture clocks, where: a timing of at least one of the one or more capture clocks is based on a first clock signal of a first clock, the first clock signal is a core clock signal or a signal derived from at least the core clock signal, the at least one of the one or more capture clocks is used to time a read data path, the at least one of the one or more capture clocks is used to capture read data into a clock domain related to a second clock, the first clock and the second clock being related in timing such that at least one of: the second clock is derived from the first clock, or the first clock is derived from the second clock; and providing access to the code.
G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 7/22 - Read-write [R-W] timing or clocking circuitsRead-write [R-W] control signal generators or management
G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G06F 1/04 - Generating or distributing clock signals or signals derived directly therefrom
G06F 1/08 - Clock generators with changeable or programmable clock frequency
G06F 1/12 - Synchronisation of different clock signals
G06F 1/14 - Time supervision arrangements, e.g. real time clock
G11C 11/4093 - Input/output [I/O] data interface arrangements, e.g. data buffers
G11C 7/04 - Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
G11C 11/40 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors
20.
Double data rate (DDR) memory controller apparatus and method
In accordance with one embodiment, an apparatus is provided, comprising: a double data rate (DDR) memory controller that, when in operation, causes the apparatus to: capture a data bit input signal in a first core domain register that is communicatively coupled to a second core domain register; clock the first core domain register utilizing a first clock; clock the second core domain register utilizing a second clock; maintain a difference in time between an active edge of the second clock and a next active edge of the first clock, such that the difference in time corresponds to a capture clock delay value; and set the capture clock delay value during a power-on initialization calibration operation.
G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 7/22 - Read-write [R-W] timing or clocking circuitsRead-write [R-W] control signal generators or management
G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G06F 1/04 - Generating or distributing clock signals or signals derived directly therefrom
G06F 1/08 - Clock generators with changeable or programmable clock frequency
G06F 1/12 - Synchronisation of different clock signals
G06F 1/14 - Time supervision arrangements, e.g. real time clock
G11C 11/4093 - Input/output [I/O] data interface arrangements, e.g. data buffers
G11C 7/04 - Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
G11C 11/40 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors
21.
Double data rate (DDR) memory controller apparatus and method
In accordance with one embodiment, an apparatus is provided, comprising: a double data rate (DDR) memory controller that, when in operation, causes the apparatus to: capture a data bit input signal in a first core domain register that is communicatively coupled to a second core domain register; clock the first core domain register utilizing a first clock; clock the second core domain register utilizing a second clock; maintain a difference in time between an active edge of the second clock and a next active edge of the first clock, such that the difference in time corresponds to a capture clock delay value; and set the capture clock delay value during a power-on initialization calibration operation.
G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
G06F 1/04 - Generating or distributing clock signals or signals derived directly therefrom
G06F 1/08 - Clock generators with changeable or programmable clock frequency
G06F 1/12 - Synchronisation of different clock signals
G06F 1/14 - Time supervision arrangements, e.g. real time clock
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 7/22 - Read-write [R-W] timing or clocking circuitsRead-write [R-W] control signal generators or management
G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
G11C 11/4093 - Input/output [I/O] data interface arrangements, e.g. data buffers
G11C 7/04 - Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
G11C 11/40 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors
22.
Double data rate (DDR) memory controller apparatus and method
In accordance with one embodiment, an apparatus is provided, comprising: a double data rate (DDR) memory controller that, when in operation, causes the apparatus to: generate a core clock; generate a capture clock; receive a data (DQ) signal that is driven by a DDR memory, or a signal derived from the DQ signal; clock a first core domain register, based, at least in part, on the capture clock; clock a second core domain register, based, at least in part, on the core clock; and set a delay of a core clock delay element, utilizing at least one of: the first core domain register, a signal derived from the first core domain register, the second core domain register, or a signal derived from the second core domain register; wherein the double data rate (DDR) memory controller is configured such that the delay of the core clock delay element is set during a power-on initialization calibration operation.
G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
G06F 1/04 - Generating or distributing clock signals or signals derived directly therefrom
G06F 1/08 - Clock generators with changeable or programmable clock frequency
G06F 1/12 - Synchronisation of different clock signals
G06F 1/14 - Time supervision arrangements, e.g. real time clock
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 7/22 - Read-write [R-W] timing or clocking circuitsRead-write [R-W] control signal generators or management
G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
G11C 11/4093 - Input/output [I/O] data interface arrangements, e.g. data buffers
G11C 7/04 - Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
G11C 11/40 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors
23.
Method for calibrating capturing read data in a read data path for a DDR memory interface circuit
A method for calibrating capturing read data in a read data path for a DDR memory interface circuit is described. In one version, the method includes the steps of delaying a core clock signal by a capture clock delay value to produce a capture clock signal and determining the capture clock delay value. The capture clock signal is a delayed version of the core clock signal. The timing for the read data path with respect to data propagation is responsive to at least the capture clock signal. In another version, timing for data capture is responsive to a read data strobe or a signal derived therefrom, and a core clock signal or a signal derived therefrom.
A method for calibrating capturing read data in a read data path for a DDR memory interface circuit is described. In one version, the method includes the steps of delaying a core clock signal by a capture clock delay value to produce a capture clock signal and determining the capture clock delay value. The capture clock signal is a delayed version of the core clock signal. The timing for the read data path with respect to data propagation is responsive to at least the capture clock signal. In another version, timing for data capture is responsive to a read data strobe or a signal derived therefrom, and a core clock signal or a signal derived therefrom.
G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
G06F 1/04 - Generating or distributing clock signals or signals derived directly therefrom
G06F 1/08 - Clock generators with changeable or programmable clock frequency
G06F 1/12 - Synchronisation of different clock signals
G06F 1/14 - Time supervision arrangements, e.g. real time clock
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 7/22 - Read-write [R-W] timing or clocking circuitsRead-write [R-W] control signal generators or management
G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
G11C 11/4093 - Input/output [I/O] data interface arrangements, e.g. data buffers
G11C 7/04 - Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
G11C 11/40 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors
25.
Continuous adaptive data capture optimization for interface circuits
A data interface circuit wherein calibration adjustments for data bit capture are made without disturbing normal system operation, is described. A plurality of DLL capture and delay circuits for sampling a trained optimal sampling point as well as leading and trailing sampling points are defined. A first stream of data bits is input to the data interface circuit and using a first calibration method and a first set of values is established. A second stream of data bits is input to the data interface circuit during normal system operation. A second calibration method is performed that is different from the first, establishing a second set of values. Several fringe timing points are sampled. A drift amount is compared with a drift correction threshold value and the first optimal sampling point is shifted in time by the drift amount to revise the first optimal sampling point.
G11C 8/18 - Address timing or clocking circuitsAddress control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
H03L 7/081 - Details of the phase-locked loop provided with an additional controlled phase shifter
H03K 5/133 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active-delay devices
H03K 5/14 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of delay lines
H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass
26.
Multiple gating modes and half-frequency dynamic calibration for DDR memory controllers
Circuits and methods are described for a DDR memory controller where two different DQS gating modes are utilized. These gating modes together ensure that the DQS signal, driven by a DDR memory to the memory controller, is only available when read data is valid. Two types of gating logic are used: Initial DQS gating logic, and Functional DQS gating logic. The Initial gating logic has additional timing margin in the Initial DQS gating value to allow for the unknown round trip timing during initial bit levelling calibration. DQS functional gating is then optimized during further calibration to gate DQS precisely as latency and phase calibration are performed, resulting in a precise gating value for Functional DQS gating. Providing dual gating modes is especially useful when data capture is performed at half the DQS frequency in view of rising clock rates for DDR memories.
G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
G06F 1/04 - Generating or distributing clock signals or signals derived directly therefrom
G06F 1/08 - Clock generators with changeable or programmable clock frequency
G06F 1/12 - Synchronisation of different clock signals
G06F 1/14 - Time supervision arrangements, e.g. real time clock
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 7/22 - Read-write [R-W] timing or clocking circuitsRead-write [R-W] control signal generators or management
G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
G11C 11/4093 - Input/output [I/O] data interface arrangements, e.g. data buffers
G11C 7/04 - Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
G11C 11/40 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors
27.
Circuit for dynamically adaptive bit-leveling by incremental sampling, jitter detection, and exception handling
A circuit and method for implementing an adaptive bit-leveling function in an integrated circuit interface is disclosed. During a calibration operation, a pre-loaded data bit pattern is continuously sent from a sending device and is continuously read from an external bus by a receiving device. A programmable delay line both advances and delays each individual data bit relative to a sampling point in time, and delay counts relative to a reference point in time are recorded for different sampled data bit values, enabling a delay to be determined that best samples a data bit at its midpoint. During the advancing and delaying of a data bit, jitter on the data bit signal may cause an ambiguity in the determination of the midpoint, and solutions are disclosed for detecting jitter and for resolving a midpoint for sampling a data bit even in the presence of the jitter.
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
G06F 1/08 - Clock generators with changeable or programmable clock frequency
H04L 1/20 - Arrangements for detecting or preventing errors in the information received using signal-quality detector
H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass
H03K 19/018 - Coupling arrangementsInterface arrangements using bipolar transistors only
28.
Multiple gating modes and half-frequency dynamic calibration for DDR memory controllers
Circuits and methods are described for a DDR memory controller where two different DQS gating modes are utilized. These gating modes together ensure that the DQS signal, driven by a DDR memory to the memory controller, is only available when read data is valid. Two types of gating logic are used: Initial DQS gating logic, and Functional DQS gating logic. The Initial gating logic has additional timing margin in the Initial DQS gating value to allow for the unknown round trip timing during initial bit levelling calibration. DQS functional gating is then optimized during further calibration to gate DQS precisely as latency and phase calibration are performed, resulting in a precise gating value for Functional DQS gating. Providing dual gating modes is especially useful when data capture is performed at half the DQS frequency in view of rising clock rates for DDR memories.
G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
G06F 1/04 - Generating or distributing clock signals or signals derived directly therefrom
G06F 1/08 - Clock generators with changeable or programmable clock frequency
G06F 1/12 - Synchronisation of different clock signals
G06F 1/14 - Time supervision arrangements, e.g. real time clock
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 7/22 - Read-write [R-W] timing or clocking circuitsRead-write [R-W] control signal generators or management
G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
G11C 7/04 - Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
G11C 11/40 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors
29.
Continuous adaptive data capture optimization for interface circuits
A continuously adaptive timing calibration function for a data interface is disclosed. A first calibration method is performed for a mission data path, typically at power-on, to establish an optimal sample point. Reference data paths are established for a second calibration method that does not disturb normal system operation. Data bit edge transitions are examined at fringe timing points on either side of the optimal sample point. Assuming that a timing change for the edge transitions indicates a drift of the optimal sample point, when a drift amount is determined to be greater than a correction threshold value the optimal sampling point for the mission path is adjusted accordingly. At no point does the continuous calibration function determine that any data bit is invalid since the optimal sampling point is always maintained. Also, at no point does continuous calibration require successive alternating data bit values such as 1-0-1 or 0-1-0.
H03K 5/13 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
H03K 5/14 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of delay lines
H03L 7/10 - Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G11C 8/18 - Address timing or clocking circuitsAddress control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
H03L 7/081 - Details of the phase-locked loop provided with an additional controlled phase shifter
H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass
30.
Methods for calibrating a read data path for a memory interface
A method for calibrating a read data path for a DDR memory interface circuit from time to time in conjunction with functional operation of a memory circuit is described. The method uses the steps of issuing a sequence of read commands so that a delayed dqs signal toggles continuously. Next, delaying a core clock signal originating within the DDR memory interface circuit to produce a capture clock signal. The capture clock signal is delayed from the core clock by a capture clock delay value. Next, determining an optimum capture clock delay value. The output of the read data path is clocked by the core clock. The timing for the read data path with respect to data propagation is responsive to at least the capture clock.
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 7/22 - Read-write [R-W] timing or clocking circuitsRead-write [R-W] control signal generators or management
G06F 1/04 - Generating or distributing clock signals or signals derived directly therefrom
G06F 1/12 - Synchronisation of different clock signals
G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 1/08 - Clock generators with changeable or programmable clock frequency
G11C 29/50 - Marginal testing, e.g. race, voltage or current testing
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 1/14 - Time supervision arrangements, e.g. real time clock
G11C 7/04 - Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
31.
CONTINUOUS ADAPTIVE TRAINING FOR DATA INTERFACE TIMING CALIBRATION
Circuits and methods for implementing a continuously adaptive timing calibration training function in an integrated circuit interface are disclosed. A mission data path is established where a data bit is sampled by a strobe. A similar reference data path is established for calibration purposes only. At an initialization time both paths are calibrated and a delta value between them is established. During operation of the mission path, the calibration path continuously performs calibration operations to determine if its optimal delay has changed by more than a threshold value. If so, the new delay setting for the reference path is used to change the delay setting for the mission path after adjustment by the delta value. Circuits and methods are also disclosed for performing multiple parallel calibrations for the reference path to speed up the training process.
A circuit and method for implementing a adaptive bit-leveling function in an integrated circuit interface is disclosed. During a calibration operation, a pre-loaded data bit pattern is continuously sent from a sending device and is continuously read from an external bus by a receiving device. A programmable delay line both advances and delays each individual data bit relative to a sampling point in time, and delay counts relative to a reference point in time are recorded for different sampled data bit values, enabling a delay to be determined that best samples a data bit at its midpoint. During the advancing and delaying of a data bit, jitter on the data bit signal may cause an ambiguity in the determination of the midpoint, and solutions are disclosed for detecting jitter and for resolving a midpoint for sampling a data bit even in the presence of the jitter.
Circuits and methods for implementing a continuously adaptive timing calibration training function in an integrated circuit interface are disclosed. A mission data path is established where a data bit is sampled by a strobe. A similar reference data path is established for calibration purposes only. At an initialization time both paths are calibrated and a delta value between them is established. During operation of the mission path, the calibration path continuously performs calibration operations to determine if its optimal delay has changed by more than a threshold value. If so, the new delay setting for the reference path is used to change the delay setting for the mission path after adjustment by the delta value. Circuits and methods are also disclosed for performing multiple parallel calibrations for the reference path to speed up the training process.
A circuit and method for implementing a adaptive bit-leveling function in an integrated circuit interface is disclosed. During a calibration operation, a pre-loaded data bit pattern is continuously sent from a sending device and is continuously read from an external bus by a receiving device. A programmable delay line both advances and delays each individual data bit relative to a sampling point in time, and delay counts relative to a reference point in time are recorded for different sampled data bit values, enabling a delay to be determined that best samples a data bit at its midpoint. During the advancing and delaying of a data bit, jitter on the data bit signal may cause an ambiguity in the determination of the midpoint, and solutions are disclosed for detecting jitter and for resolving a midpoint for sampling a data bit even in the presence of the jitter.
Circuits and methods for implementing a continuously adaptive timing calibration training function in an integrated circuit interface are disclosed. A mission data path is established where a data bit is sampled by a strobe. A similar reference data path is established for calibration purposes only. At an initialization time both paths are calibrated and a delta value between them is established. During operation of the mission path, the calibration path continuously performs calibration operations to determine if its optimal delay has changed by more than a threshold value. If so, the new delay setting for the reference path is used to change the delay setting for the mission path after adjustment by the delta value. Circuits and methods are also disclosed for performing multiple parallel calibrations for the reference path to speed up the training process.
Circuits and methods for implementing a continuously adaptive timing calibration training function in an integrated circuit interface are disclosed. A mission data path is established where a data bit is sampled by a strobe. A similar reference data path is established for calibration purposes only. At an initialization time both paths are calibrated and a delta value between them is established. During operation of the mission path, the calibration path continuously performs calibration operations to determine if its optimal delay has changed by more than a threshold value. If so, the new delay setting for the reference path is used to change the delay setting for the mission path after adjustment by the delta value. Circuits and methods are also disclosed for performing multiple parallel calibrations for the reference path to speed up the training process.
G11C 8/18 - Address timing or clocking circuitsAddress control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
H03L 7/081 - Details of the phase-locked loop provided with an additional controlled phase shifter
37.
Method for operating a circuit including a timing calibration function
Circuits and methods for implementing a continuously adaptive timing calibration training function in an integrated circuit interface are disclosed. A mission data path is established where a data bit is sampled by a strobe. A similar reference data path is established for calibration purposes only. At an initialization time both paths are calibrated and a delta value between them is established. During operation of the mission path, the calibration path continuously performs calibration operations to determine if its optimal delay has changed by more than a threshold value. If so, the new delay setting for the reference path is used to change the delay setting for the mission path after adjustment by the delta value. Circuits and methods are also disclosed for performing multiple parallel calibrations for the reference path to speed up the training process.
A calibrating memory interface circuit is described wherein prior to a calibration operation at least a portion of application information contained in a memory circuit is moved or copied to an alternate location to preserve that information. At the completion of the calibration operation, the information is restored to the same location of the memory circuit. Thus, the calibration operation can be performed from time to time during normal operation of a system containing the memory circuit. Non-limiting examples of calibration operations are described including operations where a capture clock for a memory read circuit is calibrated, and operations where CAS latency compensation is calibrated for a DDR memory interface.
A method for calibrating a memory interface circuit is described wherein prior to a calibration operation at least a portion of application information contained in a memory circuit is moved or copied to an alternate location to preserve that information. At the completion of the calibration operation, the information is restored to the same location of the memory circuit. Thus, the calibration operation can be performed from time to time during normal operation of a system containing the memory circuit. Non-limiting examples of calibration operations are described including operations where a capture clock for a memory read circuit is calibrated, and operations where CAS latency compensation is calibrated for a DDR memory interface.
A memory interface circuit for read operations is described. The circuit includes one or more controller circuits, one or more read data delay circuits for providing CAS latency compensation for byte lanes. In the system, control settings for the read data delay circuits for providing CAS latency compensation are determined and set using controller circuits according to a dynamic calibration procedure performed from time to time. In the system, determining and setting the control settings for the read data delay circuits for providing CAS latency compensation is performed independently and parallely in each of a plurality of byte lanes.
G06F 1/12 - Synchronisation of different clock signals
G06F 1/04 - Generating or distributing clock signals or signals derived directly therefrom
H03K 19/173 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components
H03K 19/00 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits
G11C 11/00 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor
G11C 8/16 - Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
G01R 35/00 - Testing or calibrating of apparatus covered by the other groups of this subclass
G01R 27/28 - Measuring attenuation, gain, phase shift, or derived characteristics of electric four-pole networks, i.e. two-port networksMeasuring transient response
G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures
G11C 29/00 - Checking stores for correct operationTesting stores during standby or offline operation
G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
G06F 1/08 - Clock generators with changeable or programmable clock frequency
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
G11C 29/50 - Marginal testing, e.g. race, voltage or current testing
G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G11C 7/22 - Read-write [R-W] timing or clocking circuitsRead-write [R-W] control signal generators or management
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 1/14 - Time supervision arrangements, e.g. real time clock
41.
Methods for operating a memory interface circuit including calibration for CAS latency compensation in a plurality of byte lanes
A method for quickly calibrating a memory interface circuit from time to time in conjunction with operation of a functional circuit is described. The method uses controlling the memory interface circuit with respect to read data capture for byte lanes, including controlling CAS latency compensation for the byte lanes. In the method control settings for controlling CAS latency compensation are determined and set according to a dynamic calibration procedure performed from time to time in conjunction with functional operation of a circuit system containing one or more memory devices connected to the memory interface circuit. In the method, determining and setting the control settings for controlling CAS latency compensation is performed independently and parallely in each of the byte lanes.
H03K 19/173 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components
H03K 19/00 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits
G11C 11/00 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor
G11C 8/16 - Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
G01R 35/00 - Testing or calibrating of apparatus covered by the other groups of this subclass
G01R 27/28 - Measuring attenuation, gain, phase shift, or derived characteristics of electric four-pole networks, i.e. two-port networksMeasuring transient response
G06F 15/00 - Digital computers in generalData processing equipment in general
G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures
G11C 29/00 - Checking stores for correct operationTesting stores during standby or offline operation
G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
G06F 1/08 - Clock generators with changeable or programmable clock frequency
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
G11C 29/50 - Marginal testing, e.g. race, voltage or current testing
G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G11C 7/22 - Read-write [R-W] timing or clocking circuitsRead-write [R-W] control signal generators or management
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 1/14 - Time supervision arrangements, e.g. real time clock
A method for calibrating a DDR memory controller is described. The method provides an optimum delay for a core clock delay element to produce an optimum capture clock signal. The method issues a sequence of read commands so that a delayed version of a dqs signal toggles continuously. The method delays a core clock signal to sample the delayed dqs signal at different delay increments until a 1 to 0 transition is detected on the delayed dqs signal. This core clock delay is recorded as “A.” The method delays the core clock signal to sample the core clock signal at different delay increments until a 0 to 1 transition is detected on the core clock signal. This core clock delay is recorded as “B.” The optimum delay value is computed from the A and B delay values.
G06F 1/04 - Generating or distributing clock signals or signals derived directly therefrom
G06F 1/12 - Synchronisation of different clock signals
H03K 19/173 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components
H03K 19/00 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits
G11C 7/00 - Arrangements for writing information into, or reading information out from, a digital store
G11C 8/16 - Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
G01F 19/00 - Calibrated capacity measures for fluids or fluent solid material, e.g. measuring cups
G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures
G11C 29/00 - Checking stores for correct operationTesting stores during standby or offline operation
G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 1/14 - Time supervision arrangements, e.g. real time clock
G06F 1/08 - Clock generators with changeable or programmable clock frequency
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
G11C 7/22 - Read-write [R-W] timing or clocking circuitsRead-write [R-W] control signal generators or management
G11C 29/50 - Marginal testing, e.g. race, voltage or current testing
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
A DDR memory controller is described wherein a core domain capture clock is created by programmably delaying the core clock of the memory controller. The delay of this capture clock is typically calibrated during a power on the initialization sequence in concert with a DDR memory in a system environment, thereby minimizing the effects of system delays and increasing both device and system yield. An additional embodiment also includes programmably delaying the incoming dqs signal. To compensate for voltage and temperature variations over time during normal operation, a runtime dynamic calibration mechanism and procedure is also provided.
G06F 1/12 - Synchronisation of different clock signals
H03K 19/173 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components
H03K 19/00 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits
G11C 11/00 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor
G11C 8/16 - Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
G01R 35/00 - Testing or calibrating of apparatus covered by the other groups of this subclass
G01R 27/28 - Measuring attenuation, gain, phase shift, or derived characteristics of electric four-pole networks, i.e. two-port networksMeasuring transient response
G06F 19/00 - Digital computing or data processing equipment or methods, specially adapted for specific applications (specially adapted for specific functions G06F 17/00;data processing systems or methods specially adapted for administrative, commercial, financial, managerial, supervisory or forecasting purposes G06Q;healthcare informatics G16H)
G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures
G11C 29/00 - Checking stores for correct operationTesting stores during standby or offline operation
G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
A DDR memory controller is described wherein a core domain capture clock is created by programmably delaying the core clock of the memory controller. The delay of this capture clock is calibrated during a power on the initialization sequence in concert with a DDR memory in a system environment, thereby minimizing the effects of system delays and increasing both device and system yield. An additional embodiment also includes programmably delaying the incoming dqs signal.
G06F 1/04 - Generating or distributing clock signals or signals derived directly therefrom
G06F 1/12 - Synchronisation of different clock signals
G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures
H03K 19/173 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components
H03K 19/00 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits
G11C 7/00 - Arrangements for writing information into, or reading information out from, a digital store
G11C 8/00 - Arrangements for selecting an address in a digital store
G11C 29/00 - Checking stores for correct operationTesting stores during standby or offline operation
G01R 35/00 - Testing or calibrating of apparatus covered by the other groups of this subclass
G01R 31/00 - Arrangements for testing electric propertiesArrangements for locating electric faultsArrangements for electrical testing characterised by what is being tested not provided for elsewhere
G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
G01B 5/02 - Measuring arrangements characterised by the use of mechanical techniques for measuring length, width, or thickness
patents
