Abstract

A process of making semiconductor-on-glass substrates having a relatively stiff (e.g. relatively high Young's modulus of 125 or higher) stiffening layer between the silicon film and the glass in an ion implantation thin film transfer process by depositing a stiffening layer or layers on one of the donor wafer or the glass substrate in order to eliminate the canyons and pin holes that otherwise form in the surface of the transferred silicon film during the thin film transfer process. The new stiffening layer may be formed of a material, such as silicon nitride, that also serves as an efficient barrier against penetration of sodium and other harmful impurities from the glass substrate into the silicon film.

IPC Classes  ?

• H01L 21/30 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups

Abstract

The invention relates to a method and to a device for at least locally heating a plate including at least one layer (2) to be at least locally heated by at least one main, light flow pulse, and including at least one priming region (4) located deeply relative to the front surface of said layer to be heated, wherein the main flow (7) is capable of heating said layer to be heated (2) while the temperature of the latter is within a high temperature range (PHT), and a priming a secondary heating means (9) capable of heating said priming region from a temperature within a low temperature range (PBT) up to a temperature within said high temperature range (PHT).

IPC Classes  ?

• F27D 11/12 - Arrangement of elements for electric heating in or on furnaces with electromagnetic fields acting directly on the material being heated
• H01L 21/268 - Bombardment with wave or particle radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
• H01L 21/22 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regionsRedistribution of impurity materials, e.g. without introduction or removal of further dopant

Abstract

A method and/or system are provided for producing a structure comprising a thin layer of semiconductor material on a substrate. The method includes creating an area of embrittlement in the thickness of a donor substrate, bonding the donor substrate with a support substrate and detaching the donor substrate at the level of the area of embrittlement to transfer a thin layer of the donor substrate onto the support substrate. The method also includes thermal treatment of this resulting structure to stabilize the bonding interface between the thin layer and the substrate support. The invention also relates to the structures obtained by such a process.

IPC Classes  ?

• H01L 21/30 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups

Abstract

A method for producing a hybrid substrate, including a support substrate, a continuous buried insulator layer and, on this continuous layer, a hybrid layer including alternating zones of a first material and at least one second material, wherein these two materials are different by their nature and/or their crystallographic characteristics. The method forms a hybrid layer, including alternating zones of first and second materials, on a homogeneous substrate, assembles this hybrid layer, the continuous insulator layer and the support substrate, and eliminates a part at least of the homogeneous substrate, before or after the assembling.

IPC Classes  ?

• H01L 21/30 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups
• H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
• H01L 21/762 - Dielectric regions
• H01L 21/8258 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using a combination of technologies covered by , , or
• H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body

Abstract

Methods of fabricating semiconductor structures and devices include bonding a seed structure to a substrate using a glass. The seed structure may comprise a crystal of semiconductor material. Thermal treatment of the seed structure bonded to the substrate using the glass may be utilized to control a strain state within the seed structure. The seed structure may be placed in a state of compressive strain at room temperature. The seed structure bonded to the substrate using the glass may be used for growth of semiconductor material, or, in additional methods, a seed structure may be bonded to a first substrate using a glass, thermally treated to control a strain state within the seed structure and a second substrate may be bonded to an opposite side of the seed structure using a non-glassy material.

IPC Classes  ?

• H01L 21/76 - Making of isolation regions between components

Abstract

2, to form therein a number of nanocavities defining a weakened zone which delimits the active layer; and transferring the active layer by applying an overall energy budget capable of causing detachment of the layer from the source substrate, wherein the budget also causes the nanocavities to grow into cavities.

IPC Classes  ?

• H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds

Abstract

The invention relates to a method for preparing a surface of a semiconductor substrate by oxidizing the surface of the semiconductor substrate to thereby transform the natural oxide into an artificial oxide and then removing the artificial oxide, in particular to obtain an oxide-free substrate surface.

IPC Classes  ?

• H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid-state devices, or of parts thereof
• H01L 21/331 - Transistors
• H01L 21/46 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups
• H01L 21/30 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups
• H01L 21/322 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to modify their internal properties, e.g. to produce internal imperfections

Abstract

A method for fabricating a semiconductor on insulator substrate by providing a first semiconductor substrate with a first impurity density of a first impurity type, subjecting the first semiconductor substrate to a first thermal treatment to thereby reduce the first impurity density in a modified layer adjacent a surface of the first semiconductor substrate being treated, transferring at least partially the modified layer with the reduced first impurity density onto a second substrate, to thereby obtain a modified second substrate, and providing a further layer on a transferred layer of the modified second substrate with the further layer having a second impurity density of a second impurity type that is different than the first impurity type of the transferred modified layer. By doing so, a contamination by dopants of the second impurity type of a fabrication line using semiconductor material with dopants of the first impurity type, can be prevented.

IPC Classes  ?

• H01L 21/46 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups

Abstract

A method for transferring a thin layer from a lithium-based first substrate includes proton exchange between the first substrate and a first electrolyte, which is an acid, through a free face of the first substrate so as to replace lithium ions of the first substrate by protons, in a proportion between 10% and 80%, over a first depth e1. A reverse proton exchange between the first substrate and a second electrolyte, through the free face is carried out so as to replace substantially all the protons with lithium ions over a second depth e2 smaller than the first depth e1, and so as to leave an intermediate layer between the depths e1 and e2, in which intermediate layer protons incorporated during the proton exchange step remain. The depth e2 defines a thin layer between the free face and the intermediate layer. A heat treatment is carried out under conditions suitable for embrittling the intermediate layer and the thin film is separated from the first substrate at the intermediate layer.

IPC Classes  ?

• G02B 6/10 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type

Abstract

Methods of fabricating photovoltaic devices include forming a plurality of subcells in a vertically stacked arrangement on the semiconductor material, each of the subcells being formed at a different temperature than an adjacent subcell such that the adjacent subcells have differing effective band gaps. The methods of fabricating also include inverting the structure, attaching another substrate to the second semiconductor material, and removing the substrate. For example, each of the subcells may comprise a III nitride material, and each subsequent subcell may include an indium content different than the adjacent subcell. Novel structures may be formed using such methods.

IPC Classes  ?

• H01L 31/0304 - Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds
• H01L 31/0352 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
• H01L 31/04 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices
• H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

Abstract

A method for producing an epitaxial layer. First, a structure is fabricated by: formation of an intermediate layer on a donor substrate; and formation of the epitaxial layer on the intermediate layer by epitaxy; with the melting temperature of the intermediate layer being lower than the melting temperature of the epitaxial layer; and then a detachment step for transferring the epitaxial layer from the donor substrate. The detachment step includes applying at least one thermal treatment performed at a temperature of between the melting temperature of the intermediate layer and the melting temperature of the epitaxial layer.

IPC Classes  ?

• H01L 21/30 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups

Abstract

A structure and a method can provide forming a structure for a crystalline seed layer material, such as GaN, on a crystalline carrier material, such as sapphire, aligned such that a common crystal plane exists between the two materials. The common crystal plane may provide for a fracture surface along a cleavage plane that may be oriented to be perpendicular to the top surface of an optoelectronic device as well as perpendicular to a light emission direction.

IPC Classes  ?

• H01S 5/323 - Structure or shape of the active regionMaterials used for the active region comprising PN junctions, e.g. hetero- or double- hetero-structures in AIIIBV compounds, e.g. AlGaAs-laser
• H01S 5/343 - Structure or shape of the active regionMaterials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser

Abstract

A method for manufacturing a hybrid semiconductor substrate comprises the steps of (a) providing a hybrid semiconductor substrate comprising a semiconductor-on-insulator (SeOI) region, that comprises an insulating layer over a base substrate and a SeOI layer over the insulating layer, and a bulk semiconductor region, wherein the SeOI region and the bulk semiconductor region share the same base substrate; (b) providing a mask layer over the SeOI region; and (c) forming a first impurity level by doping the SeOI region and the bulk semiconductor region simultaneously such that the first impurity level in the SeOI region is contained within the mask. Thereby, a higher number of process steps involved in the manufacturing process of hybrid semiconductor substrates may be avoided.

IPC Classes  ?

• H01L 21/425 - Bombardment with radiation with high-energy radiation producing ion implantation
• H01L 21/70 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereofManufacture of integrated circuit devices or of specific parts thereof

Abstract

The invention concerns a method to thin an initial silicon-on-insulator SOI substrate, comprising a layer (3) of silicon oxide SiO2 buried between a silicon carrier substrate (2) and a silicon surface layer. This method is noteworthy in that it comprises the following successive steps consisting of conducting: -thermal oxidation treatment of said initial substrate, to oxidize part of said silicon surface layer, -a first, then a second cycle of etching and cleaning, the first cycle etching being performed so as fully to remove the formed thermal oxide and to lift off all the unstable parts of the edge of said initial substrate, the second cycle etch being conducted to remove from the surface of said thinned substrate the formed polluting particles (5) deposited thereupon, so as to obtain a final SOI substrate (1') whose thinned surface layer (4') forms an active layer.

IPC Classes  ?

• H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
• H01L 21/762 - Dielectric regions

Abstract

3 which is in between the first and second lattice parameters.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

The invention provides methods and structures for reducing surface dislocations of a semiconductor layer, and can be employed during the epitaxial growth of semiconductor structures and layers comprising Ill-nitride materials. Embodiments involve the formation of a plurality of dislocation pit plugs to prevent propagation of dislocations from an underlying layer of material into a following semiconductor layer of material.

IPC Classes  ?

• H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

A process for reducing or suppressing the appearance of watermarks in a hydrophobic surface of a semiconductor substrate prepared as a base substrate for epitaxial growth. The process includes cleaning the hydrophobic surface of the semiconductor substrate with an aqueous solution containing hydrofluoric acid (HF) and an additional acid having a pKa of less than 3, preferably hydrochloric acid (HCl), wherein the additional acid is present in the solution at a concentration by weight that is less than that of the HF; and final rinsing the cleaned hydrophobic surface of the semiconductor substrate with deionised water while subjecting the hydrophobic surface of the semiconductor substrate to megasonic waves for a time sufficient to reduce or suppress watermarks that could otherwise occur on the hydrophobic surface if the megasonic waves were not applied.

IPC Classes  ?

• H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth

Abstract

The invention concerns a finishing method for a substrate (1) of silicon-on-insulator SOI type, comprising an oxide layer (3) buried between an active silicon layer (4) and a support layer(2) in silicon, this method comprising the application of finishing steps whose successive steps are:a)rapid thermal annealing RTA of said substrate (1) b)sacrificial oxidation step of its active layer (4), c)rapid thermal annealing RTA of said substrate obtained after step (b), d)sacrificial oxidation step of said active layer of the substrate (1') which underwent step c), this method being characterized in that sacrificial oxidation step b) is conducted so as to remove a first oxide thickness (5) and in that sacrificial oxidation step d) is conducted so as to remove a second oxide thickness thinner than the first.

IPC Classes  ?

• H01L 21/762 - Dielectric regions

Abstract

The invention relates to a method for finishing the surface of semiconducting substrate (1), said substrate comprising a set of layers comprising a useful semiconducting layer (4) on at least one of the faces of said substrate (1), said useful layer (4) comprising a rough free surface (7), said method being suitable for smoothing out the free surface (7), said method being characterized in that it comprises the successive steps of : - creating a protective layer (20) covering the surface (7) of the useful layer (4) with a thickness 1 to 3 times larger than the peak-to-valley distance of said surface (7) of the useful layer (4), - at least one polishing-oxidation sequence, said sequence comprising the successive steps of : polishing the surface (21) of the protective layer (20), said polishing being adjusted so as not to attack the useful layer (4), and performing a thermal oxidation with supply of oxygen gas of the substrate (1), in order to transform a portion of the useful layer (4) into an oxide layer (16), in order to reduce the roughness of the surface (7) of the useful layer (4).

IPC Classes  ?

• H01L 21/302 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
• H01L 21/762 - Dielectric regions

Abstract

A method of producing a heterostructure (200) comprising bonding at least one first substrate (110) having a first thermal expansion coefficient onto a second substrate (120) having a second thermal expansion coefficient, the first thermal expansion coefficient being different from the second thermal expansion coefficient. Prior to bonding, trenches (111) are formed in one of the two substrates from the bonding surface (110a) of the substrate (110). The trenches (111) are filled with a material (130) having a third thermal expansion coefficient lying between the first and second thermal expansion coefficients.

IPC Classes  ?

• H01L 21/62 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having no potential barriers

Abstract

A method of producing a composite structure comprises a step of producing a first layer of microcomponents (110) on one face of a first substrate (100), the first substrate being held flush against a holding surface (121a) of a first support (121) during production of said microcomponents (110), and a step of bonding the face of the first substrate (100) comprising the layer of microcomponents (110) onto a second substrate (200). During the bonding step, the first substrate (100) is held flush against a second support (221) the holding surface (221a) of which has a flatness that is less than or equal to that of the first support (120) used during production of the first layer of microcomponents (110).

IPC Classes  ?

• H01L 21/762 - Dielectric regions

Abstract

The invention relates to a method of adapting the lattice parameter of a seed layer (3) of a strained material, comprising the following successive steps: a) a structure (10) is provided that has a seed layer (3) of strained material, of lattice parameter A1, of nominal lattice parameter An and of thermal expansion coefficient CTE3, a low viscosity layer (2) and an intermediate substrate (1 ) of thermal expansion coefficient CTE1; b) a heat treatment is applied so as to relax the seed layer (3) of strained material; and c) the seed layer (3) is transferred onto a support substrate (5) of thermal expansion coefficient CTE5, the intermediate substrate (1 ) and the support substrate (5) being chosen so that A1 < An and CTE1 < CTE3 and CTE5 > CTE1 or A1 > An and CTE1≥ CTE3 and CTE5 < CTE1

IPC Classes  ?

• H01L 21/762 - Dielectric regions

Abstract

The invention relates to a method for manufacturing a heterostructure, notably intended for applications in the fields of electronics, photovoltaics, optics or optoelectronics, which comprises the following steps: - implantation of atomic species inside a first so-called "donor" substrate (1), so as to form an embrittlement area (11) therein, - assembly of a second so-called "receiver" substrate (3), on the donor substrate (1), - detachment of the rear portion of said donor substrate (1) along the embrittlement area (11) so as to individualize a thin layer of interest (12) on the receiver substrate, wherein said receiver substrate (3) has a larger thermal expansion coefficient than that of the donor substrate (1), and which applies so-called "detachment" annealing after said assembly and before said detachment, in order to facilitate the latter, characterized by the fact that said detachment annealing comprises simultaneous application: - of a first temperature to the donor substrate (1); - of a second temperature, different from the first, to the receiver substrate (3); these first and second temperatures being selected so as to reduce the tensile stress condition of the donor substrate (1).

IPC Classes  ?

• H01L 21/762 - Dielectric regions

Abstract

The present invention provides improved gas injectors for use with CVD (chemical vapour deposition) systems that thermalize gases prior to injection into a CVD chamber. The provided injectors are configured to increase gas flow times through heated zones and include gas-conducting conduits that lengthen gas residency times in the heated zones. The provided injectors also have outlet ports sized, shaped, and arranged to inject gases in selected flow patterns. The invention also provides CVD systems using the provided thermalizing gas injectors. The present invention has particular application to high volume manufacturing of GaN substrates.

IPC Classes  ?

• C23C 16/34 - Nitrides
• C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
• C30B 23/06 - Heating of the deposition chamber, the substrate, or the materials to be evaporated
• C30B 25/14 - Feed and outlet means for the gasesModifying the flow of the reactive gases

Abstract

The present invention relates to an etching composition, in particular for silicon materials, a method for characterizing defects on surfaces of such materials and a process of treating such surfaces with the etching composition, wherein the etching composition comprises an organic oxidant dissolved in a solvent, and a de-oxidant, wherein the de-oxidant comprises HF or HBF4 or mixtures thereof.

IPC Classes  ?

• C09K 13/08 - Etching, surface-brightening or pickling compositions containing an inorganic acid containing a fluorine compound

Abstract

The invention relates to a method for manufacturing components on a mixed substrate. It comprises the following steps: providing a substrate (1) of the semiconductor-on-insulator (SeOI) type comprising a buried oxide layer (12) between a supporting substrate (11) and a thin layer (13), forming in this substrate (1) a plurality of trenches (3, 3') opening out at the free surface (130) of said thin layer (13) and extending over a depth such that it passes through said thin layer (13) and said buried oxide layer (12), these primary trenches (3, 3') delimiting at least one island (30) of said SeOI substrate (1), forming a mask (4) inside said primary trenches (3, 3') and as a layer covering the areas of the free surface (130) of said thin layer (13) located outside said islands (30), proceeding with heat treatment for dissolving the buried oxide layer present at said island (30), so as to reduce the thickness thereof.

IPC Classes  ?

• H01L 21/762 - Dielectric regions

Abstract

The present invention relates a method for the formation of an at least partially relaxed strained material layer, the method comprising the steps of providing a seed substrate; patterning the seed substrate; growing a strained material layer on the patterned seed substrate; transferring the strained material layer from the patterned seed substrate to an intermediate substrate; and at least partially relaxing the strained material layer by a heat treatment.

IPC Classes  ?

• H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
• H01L 21/762 - Dielectric regions
• C30B 29/38 - Nitrides
• C30B 33/02 - Heat treatment
• C30B 33/06 - Joining of crystals
• C30B 29/40 - AIIIBV compounds
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

A method of producing a layer of cavities in a structure (100) comprises at least one substrate (101) formed from a material that can be oxidized or nitrided, the method comprising the following steps: implanting ions (10) into said substrate (101) in order to form an implanted ion concentration zone (102) at a predetermined mean depth; heat treating the implanted substrate to form a layer of cavities (103) at the implanted ion concentration zone (102); and forming an insulating layer (105) in said substrate by thermochemical treatment from one surface of said substrate, said insulating layer that is formed extending at least partially into the layer of cavities (103).

IPC Classes  ?

• H01L 21/762 - Dielectric regions

Abstract

Methods and structures for producing semiconductor materials, substrates and devices with improved characteristics are disclosed. Structures and methods for forming reduced strain structures include forming a plurality of substantially strain relaxed island structures and utilizing such island structures for subsequent further growth of strain relaxed substantial continuous layers of semiconductor material.

IPC Classes  ?

• H01L 21/205 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth using reduction or decomposition of a gaseous compound yielding a solid condensate, i.e. chemical deposition

Abstract

An apparatus for measuring a lifetime of charge carriers that has a measuring probe and a component for directing ultraviolet radiation to a measuring position. The measuring probe also includes at least one electrode provided at a predetermined spatial relationship to the measuring position. A microwave source is adapted to direct microwave radiation to the measuring position, a microwave detector is adapted to measure an alteration of an intensity of microwave radiation reflected at the measuring position in response to the ultraviolet radiation and a semiconductor structure holder is adapted to receive a semiconductor structure and to provide an electric contact to a portion of the semiconductor structure. Additionally, a device for moving the substrate holder relative to the measuring probe is provided for positioning at least one portion of the semiconductor structure at the measuring position. The apparatus includes a power source adapted to apply a bias voltage between the semiconductor structure holder and the electrode.

IPC Classes  ?

• G01R 27/32 - Measuring attenuation, gain, phase shift, or derived characteristics of electric four-pole networks, i.e. two-port networksMeasuring transient response in circuits having distributed constants

Abstract

The invention concerns a process to treat a structure of semiconductor-on-insulator type, successively comprising a carrier substrate, an oxide layer (2) and a thin layer of a semiconductor material (3), said structure having a peripheral ring in which the oxide layer (2) is exposed, said process comprising application of a main thermal treatment in a neutral or controlled reducing atmosphere. It comprises a step to cover at least an exposed peripheral part of the oxide layer (2), prior to said main thermal treatment, this latter treatment being conducted under controlled time and temperature conditions so as to urge at least part of the oxygen in the oxide layer (2) to diffuse through the thin semiconductor layer (3), leading to controlled reduction of the thickness of the oxide layer (2).

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 21/3105 - After-treatment
• H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Abstract

The invention relates to a test method comprising an electrical connection contact on the support (2) of a substrate of the "semiconductor on insulator" type (1). This method is remarkable in that it comprises the steps of : a) taking a substrate (1) of the "semiconductor on insulator" type comprising a support substrate (2) entirely covered with an insulator layer (3) and an active layer (4), a portion (31) of said insulator layer (3) being buried between the active layer and the front face (21) of the support substrate (2), b) removing a portion of said insulator layer (3) which extends at the periphery of the front face (21) of the support substrate (2) and/or which extends on its rear face (22), so as to delimit at least one insulator-free accessible area (210) of the support substrate (2), while retaining at least one portion (321) of the insulator layer on the rear face, c) applying an electrical voltage to said accessible area (210), in order to make said electrical connection contact.

IPC Classes  ?

• H01L 21/66 - Testing or measuring during manufacture or treatment

Abstract

A process for splitting a semiconductor substrate having an identification notch on its periphery, by creating a weakened zone in the substrate by implanting atomic species into the substrate while the substrate is held in place on a portion of its periphery during the implanting; and splitting the substrate along the weakened zone by placing the held portion of the substrate in a splitting-wave initiation sector while positioning the notch for initiating a splitting wave followed by the propagation of the wave into the substrate. During splitting the notch is positioned so that it is in a quarter of the periphery of the substrate diametrically opposite the sector for initiating the splitting wave or in the quarter of the periphery of the substrate that is centered on the sector.

IPC Classes  ?

• H01L 21/30 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups

Abstract

a step of assembling said semiconductor layer with a second support.

IPC Classes  ?

• H01L 29/786 - Thin-film transistors

Abstract

The invention relates to a method of fabricating a back-illuminated image sensor comprising the steps of providing a first substrate comprising a semiconductor layer, in particular a silicon layer, forming electronic device structures over the semiconductor layer and, only then, doping the semiconductor layer. By doing so, improved dopant profiles and electrical properties of photodiodes can be achieved such that the final product, namely an image sensor, has a better quality.

IPC Classes  ?

• H01L 27/146 - Imager structures

Abstract

A method is described for thinning a structure (200) comprising at least two wafers (201, 202) assembled one with the other, one (202) of the two wafers including channels (203) on its surface (202a) facing the other wafer (201). In order to cause thinning of the structure, a fluid is introduced into the channels (203) in a supercritical state and the fluid is passed from the supercritical state into the gaseous state. The method is also characterized in that the channels (203) do not open to the outside of the structure, the method further comprising forming from the outer surface of the structure, before introducing the fluid in the supercritical state, at least one access opening (204) to the channels (203).

IPC Classes  ?

• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials

Abstract

Composite substrates are produced that include a strained Ill-nitride material seed layer on a support substrate. Methods of producing the composite substrate include developing a desired lattice strain in the Ill-nitride material to produce a lattice parameter substantially matching a lattice parameter of a device structure to be formed on the composite substrate. The Ill-nitride material may be formed with a Ga polarity or a N polarity. The desired lattice strain may be developed by forming a buffer layer between the Ill-nitride material and a growth substrate, implanting a dopant or introducing an impurity in the Ill-nitride material to modify its lattice parameter, or forming the Ill-nitride material with a coefficient of thermal expansion (CTE) on a growth substrate with a different CTE.

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
• H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth

Abstract

The invention relates to a method for manufacturing a heterostructure, particularly for use in the electronic, optical, or optoelectronic fields, said method including the following steps: implanting atomic species inside a first so-called "donor" substrate (7) so as to form an embrittlement area (71) therein; assembling a second so-called "recipient" substrate (R) on the donor substrate; detaching the rear portion of said donor substrate along the embrittlement area (71) so that a thin layer of interest is customized on the recipient substrate (R), characterized in that an ingot (7) or an ingot section formed from at least two basic ingots assembled together along two of the respective complementary longitudinal surfaces thereof is used as the donor substrate.

IPC Classes  ?

• C30B 29/06 - Silicon
• C30B 33/06 - Joining of crystals
• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• C30B 29/08 - Germanium
• H01L 21/762 - Dielectric regions

Abstract

The invention relates to a method of fabricating a heterostructure comprising at least a first substrate (120) made of sapphire and a second substrate (110) made of a material having a coefficient of thermal expansion that is different from that of the first substrate, the method including a step (S6) of molecular bonding the second substrate (110) on the first substrate (120) made of sapphire. In accordance with the invention, the method includes, prior to bonding the two substrates together, a step (S1) of stoving the first substrate (120) at a temperature that lies in the range 100°C to 500°C.

IPC Classes  ?

• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• H01L 21/762 - Dielectric regions

Abstract

The invention provides a method of producing a heterostructure of the silicon-on-sapphire type, comprising bonding an SOI substrate (110) onto a sapphire substrate (120) and thinning the SOI substrate, thinning being carried out by grinding followed by etching of the SOI substrate (110). In accordance with the method, grinding is carried out using a wheel (210) with a grinding surface (211) that comprises abrasive particles having a mean dimension of more than 6.7 urn; further, after grinding and before etching, said method comprises a step of post-grinding annealing of the heterostructure carried out at a temperature in the range 150 °C to 170 °C.

IPC Classes  ?

• H01L 21/762 - Dielectric regions

Abstract

Methods which can be applied during the epitaxial growth of semiconductor structures and layers of III-nitride materials so that the qualities of successive layers are successively improved. An intermediate epitaxial layer is grown on an initial surface so that growth pits form at surface dislocations present in the initial surface. A following layer is then grown on the intermediate layer according to the known phenomena of epitaxial lateral overgrowth so it extends laterally and encloses at least the agglomerations of intersecting growth pits. Preferably, prior to growing the following layer, a discontinuous film of a dielectric material is deposited so that the dielectric material deposits discontinuously so as to reduce the number of dislocations in the laterally growing material. The methods of the invention can be performed multiple times to the same structure. Also, semiconductor structures fabricated by these methods.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

Methods of fabricating semiconductor devices or structures include forming structures of a semiconductor material overlying a layer of a compliant material, subsequently changing the viscosity of the compliant material to relax the semiconductor material structures, and utilizing the relaxed semiconductor material structures as a seed layer in forming a continuous layer of relaxed semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a continuous layer of semiconductor material having a relaxed lattice structure.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

A method of bonding a first substrate (210) on a second substrate (220) by molecular bonding, the method comprising the following steps: • forming a layer of insulation (212) on the bonding face (210a) of the first substrate (210); • chemical -mechanical polishing said layer of insulation (212); • activating the bonding surface of the second substrate (220) by plasma treatment; and • bonding together the two substrates (210, 220) by molecular bonding; the method being characterized in that it further comprises, after the chemical -mechanical polishing step and before the bonding step, a step of etching the surface (212a) of the layer of insulation (212) formed on the first substrate.

IPC Classes  ?

• C03C 15/00 - Surface treatment of glass, not in the form of fibres or filaments, by etching
• C03C 17/22 - Surface treatment of glass, e.g. of devitrified glass, not in the form of fibres or filaments, by coating with other inorganic material
• C03C 27/06 - Joining glass to glass by processes other than fusing

Abstract

The invention relates to a method and to a device for at least locally heating a plate including at least one layer (2) to be at least locally heated by at least one main light flow pulse, and including at least one priming area (4) located deeply relative to the front surface of said layer to be heated, wherein the main flow (7) is capable of heating said layer to be heated (2) when the temperature of the latter is within a high temperature range (PHT), and a priming a secondary heating means (9) capable of heating said priming region from a temperature within a low temperature range (PBT) up to a temperature within said high temperature range (PHT).

IPC Classes  ?

• H01L 21/22 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regionsRedistribution of impurity materials, e.g. without introduction or removal of further dopant
• H01L 21/268 - Bombardment with wave or particle radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
• H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

Abstract

The present invention notably concerns a method to fabricate and treat a structure of semiconductor-on-insulator type, successively comprising a carrier substrate (1), an oxide layer (3) and a thin layer (2) of semiconducting material, according to which: 1) a mask is formed on said thin layer (2) so as to define exposed regions (20), on the surface of said layer, which are not covered by the mask; 2) heat treatment is applied so as to urge at least part of the oxygen of the oxide layer (3) to diffuse through the thin layer (2), leading to controlled removal of the oxide in the regions (30) of the oxide layer (3) corresponding to the desired pattern; characterized in that said carrier substrate (1) and thin layer (2) are arranged relative to each other so that their crystal lattices, in a plane parallel to their interface (I), together form an angle called a "twist angle" of no more than 1°, and in a plane perpendicular to their interface (I) an angle called a "tilt angle" of no more than 1°, and in that a thin layer (2) is used whose thickness is less than 1100 Å.

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Abstract

Method for producing stacked UTBOX-like semi-conductor structures, said method comprising: a) the formation of an electrical insulator layer on a donor substrate, b) the introduction of elements into the donor substrate through the insulator layer, c) the formation of an electrical insulator layer, on a second substrate known as final substrate, d) the bonding of the two substrates, the two insulator layers limiting the diffusion of water and forming an insulator layer buried between the two substrates, of thickness less than 50 nm, the donor oxide layer having, during the bonding, a thickness at least equal to that of the bonding oxide layer.

IPC Classes  ?

• H01L 21/762 - Dielectric regions

Abstract

The invention relates to a method for producing UTBOX type structures comprising: a) the assembly of a substrate, known as "donor" substrate (1), with a substrate, known as "receiver" substrate (2), at least one of the two substrates comprising an insulating layer (3) of thickness less than 50 nm, b) a first heat treatment for reinforcing the assembly between the two substrates, at temperature below 400°C, carried out during the assembly and/or after assembly, to reinforce said assembly, c) a second heat treatment at temperature above 900°C, the exposure time between 400°C and 900°C being less than 1 minute or 30 seconds.

IPC Classes  ?

• H01L 21/762 - Dielectric regions

Abstract

A method of detaching two substrates at the embrittlement zone situated at a given depth of one of the two substrates. The method includes a separation annealing step implemented in a furnace, wherein the annealing includes a first phase during which the temperature changes along an upgrade allowing a high temperature to be reached and annealing at this high temperature to be stabilized, and a second phase during which the temperature changes along a downgrade, at the end of which the furnace is opened to unload the substrates from the furnace. The second phase is regulated so as to minimize temperature inhomogeneities such as cleavage defects at the detached surfaces of the substrates when the furnace is opened.

IPC Classes  ?

• H01L 21/30 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups

Abstract

The invention relates to methods of fabricating a layer of at least partially relaxed material, such as for electronics, optoelectronics or photovoltaics. An exemplary method includes supplying a structure that includes a layer of strained material situated between a reflow layer and a stiffener layer. The method further includes applying a heat treatment that brings the reflow layer to a temperature equal to or greater than the glass transition temperature of the reflow layer, and the thickness of the stiffener layer is progressively reduced during heat treatment. The invention also relates to an exemplary method of fabricating semiconductor devices on a layer of at least partially relaxed material. Specifically, at least one active layer may be formed on the at least partially relaxed material layer. The active layer may include laser components, photovoltaic components and/or electroluminescent diodes.

IPC Classes  ?

• H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
• H01L 21/36 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth

Abstract

The invention relates to a process for treating a semiconductor-on- insulator type structure, successively comprising a support substrate (1 ), an oxide layer (2) and a thin semiconductor layer (3), said process comprising the following steps: (a) formation of a silicon nitride or silicon oxinitride mask (4) on the thin semiconductor layer (3), so as to define so-called exposed areas (3a) at the surface of said layer (3), which are not covered by the mask (40, and which are arranged in a desired pattern, (b) application of a heat treatment in a neutral or controlled reducing atmosphere, and under controlled conditions of temperature and time, so as to induce at least a portion of the oxygen of the oxide layer (2) to diffuse through the thin semiconductor layer (3), thereby resulting in the controlled reduction in the oxide thickness in the areas (2a) of the oxide layer corresponding to said desired pattern. In step (a), the mask (4) is formed so as to be at least partially buried in the thickness of the thin semiconductor layer (3).

IPC Classes  ?

• H01L 21/762 - Dielectric regions

Abstract

A composite substrate for laser devices is disclosed having improved wave guiding properties, improved lattice matching, improved thermal expansion matching, and improved thermal conductivity. The composite substrate has an intermediate layer (110) formed on a support substrate (102), and a seed layer (120) formed on the intermediate layer. An active device layer (124) is grown or attached to the seed layer, or to a light confinement layer on the seed layer. The intermediate layer may be formed directly on the support layer, or may be formed by thinning an attached wafer of the intermediate material, which is then thinned to a desired thickness.

IPC Classes  ?

• H01S 5/02 - Structural details or components not essential to laser action
• H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

Methods of fabricating relaxed layers of semiconductor materials include forming structures of a semiconductor material overlying a layer of a compliant material, and subsequently altering a viscosity of the compliant material to reduce strain within the semiconductor material. The compliant material may be reflowed during deposition of a second layer of semiconductor material. The compliant material may be selected so that, as the second layer of semiconductor material is deposited, a viscosity of the compliant material is altered imparting relaxation of the structures. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Methods of fabricating semiconductor structures and devices are also disclosed. Novel intermediate structures are formed during such methods. Engineered substrates include a plurality of structures comprising a semiconductor material disposed on a layer of material exhibiting a changeable viscosity.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

The invention relates to a method of trimming a structure (500) comprising a first wafer (200) bonded to a second wafer (300), the first wafer (200) having a chamfered edge. The method comprises a first step (S4) for trimming the edge of the first wafer (200) carried out by mechanical machining over a predetermined depth (Pd1) in the first wafer. This first trimming step is followed by a second step (S5) for non-mechanical trimming over at least the remaining thickness of the first wafer.

IPC Classes  ?

• H01L 21/302 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting

Abstract

The invention provides a method of trimming a structure (500) comprising a first wafer (200) bonded to a second wafer (300), the first wafer having a chamfered edge. The method comprises a first trimming step (S4) carried out over a first depth (Pd1) comprising the thickness (e1) of the first wafer (101) and over a first width (1d1) determined from the edge of the first wafer (101). A second trimming step (S5) is also carried out over a second depth (Pd2) comprising at least the thickness (e1) of the first wafer (101) and over a second width (1d2) that is less than the first width (1d1).

IPC Classes  ?

• H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting

Abstract

The present invention relates to a method for relaxing a strained material layer, comprising providing a strained material layer and a low-viscosity layer formed on a first face of the strained material layer; forming a stiffening layer on at least one part of a second face of the strained material layer opposite to the first face thereby forming a multilayer stack; and subjecting the multilayer stack to a heat treatment thereby at least partially relaxing the strained material layer.

IPC Classes  ?

• H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
• H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth

Abstract

The invention relates to a method of initiating molecular bonding, comprising bringing one face (31) of a first wafer (30) to face one face (21) of a second wafer (20) and initiating a point of contact between the two facing faces. The point of contact is initiated by application to one of the two wafers, for example using a bearing element (51) of a tool (50), of a mechanical pressure in the range 0,1 MPa to 33.3 MPa.

IPC Classes  ?

• H01L 21/762 - Dielectric regions

Abstract

2 and the thinning is an oxidation step conducted at a temperature of less than 925° C.

IPC Classes  ?

• H01L 21/762 - Dielectric regions

Abstract

Methods of fabricating semiconductor devices or structures include bonding a layer of semiconductor material to another material at a temperature, and subsequently changing the temperature of the layer of semiconductor material. The another material may be selected to exhibit a coefficient of thermal expansion such that, as the temperature of the layer of semiconductor material is changed, a controlled and/or selected lattice parameter is imparted to or retained in the layer of semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a layer of semiconductor material having an average lattice parameter at room temperature proximate an average lattice parameter of the layer of semiconductor material previously attained at an elevated temperature.

IPC Classes  ?

• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• H01L 21/762 - Dielectric regions
• H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof

Abstract

A semiconductor growth system includes a chamber and a source of electromagnetic radiation. A detector is arranged to detect absorption of radiation from the source by a chloride- based chemical of the reaction chamber. A control system controls the operation of the chamber in response to the absorption of radiation by the chloride-based chemical. The control system controls the operation of the chamber by adjusting a parameter of the reaction chamber.

IPC Classes  ?

• C23C 16/52 - Controlling or regulating the coating process
• C30B 25/16 - Controlling or regulating
• C30B 29/40 - AIIIBV compounds
• C23C 16/30 - Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides

Abstract

The present invention provides methods for relaxing a strained-material layer and structures produced by the methods. Briefly, the methods include depositing a first low-viscosity layer that includes a first compliant material on the strained-material layer, depositing a second low-viscosity layer that includes a second compliant material on the strained-material layer to form a first sandwiched structure and subjecting the first sandwiched structure to a heat treatment such that the reflow of the first and the second low-viscosity layers permits the strained-material layer to at least partly relax.

IPC Classes  ?

• H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid-state devices, or of parts thereof

Abstract

The present invention relates to a method for passivation of a semiconductor structure, comprising the steps providing at least one first material layer; forming at least one second material layer that is to be patterned above the first material layer; forming a diffusion barrier layer between the at least one second material layer and the at least one first material layer thereby forming a multilayer stack and patterning, in particular, etching, the at least one second material layer down to but not completely through the diffusion barrier layer and without exposing portions of the at least one first material layer such that diffusion of material of the at least one first material layer through the diffusion barrier layer during a subsequent heat treatment of the multilayer stack is substantially prevented. The invention also relates to a method for passivation of a semiconductor structure, comprising the steps providing a multilayer stack comprising at least one buried layer formed below a second material layer; patterning, in particular, etching, the surface of the multilayer stack through the second material layer thereby exposing portions of the at least one buried layer and depositing a diffusion barrier layer at least on the exposed portions of the at least one buried layer such that diffusion of material of the at least one buried layer through the diffusion barrier layer during a subsequent heat treatment of the multilayer stack is substantially prevented.

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
• H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth

Abstract

The present invention relates a method for the formation of at least partially relaxed strained material on a target substrate, comprising the subsequently performed steps of forming islands from a strained material layer on an intermediate substrate, at least partially relaxing the strained material islands by a first heat treatment and transferring the at least partially relaxed strained material islands to the target substrate.

IPC Classes  ?

• H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
• H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
• H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
• H01L 21/58 - Mounting semiconductor devices on supports
• H01L 21/762 - Dielectric regions

Abstract

The present invention relates to a method for relaxing a strained material layer, comprising depositing a first low-viscosity layer comprising a first compliant material on the strained material layer, depositing a second low-viscosity layer comprising a second compliant material on the strained material layer to form a first sandwiched structure and subjecting the first sandwiched structure to a heat treatment such that reflow of the first and the second low-viscosity layers is caused thereby at least partly relaxing the strained material layer.

IPC Classes  ?

• H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
• H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
• H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
• H01L 33/32 - Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
• B01J 3/06 - Processes using ultra-high pressure, e.g. for the formation of diamondsApparatus therefor, e.g. moulds or dies
• B01J 3/00 - Processes of utilising sub-atmospheric or super-atmospheric pressure to effect chemical or physical change of matterApparatus therefor

Abstract

The present invention relates to a method for making a structure notably intended for applications in the fields of electronics, optics or optoelectronics, which comprises a thin layer (1) of semiconducting material on a supporting substrate (3), according to which: a) said thin layer (1) is adhesively bonded on said supporting substrate (3) by molecular adhesion; b) said thereby obtained structure is heat-treated in order to stabilize the adhesive bonding interface (2), characterized by the fact that prior to step b), it is proceeded with an implantation of ions at said interface (2), so as to transfer atoms from the thin layer (1) to the supporting substrate (3), and/or from the supporting substrate (3) to the thin layer (1).

IPC Classes  ?

• H01L 21/762 - Dielectric regions

Abstract

The invention relates to a method of implanting atoms and/or ions into a substrate, comprising: a) a first implantation of ions or atoms at a first depth in the substrate, in order to form a first implantation plane, b) at least one second implantation of ions or atoms at a second depth in the substrate, which is different from the first depth, in order to form at least one second implantation plane.

IPC Classes  ?

• H01L 21/762 - Dielectric regions

Abstract

The invention relates to a process for modifying a substrate (10) comprising: (a) providing an initial substrate (10) having a face (10b) for bonding and an opposing face (10r); (b) providing a support substrate (25); wherein either the bonding face (10b) of the initial substrate (10), and/or a face of the support substrate (25), is provided with an electromagnetic radiation absorbing layer (24), wherein the support substrate (25) is substantially transparent to a wavelength of electromagnetic radiation (c) performing bonding to join the bonding face (10b) of the initial substrate (10) to the support substrate (25) via the electromagnetic radiation absorbing layer (24); (e) carrying out irradiation of the electromagnetic radiation absorbing layer (24) through the substantially transparent support substrate (25) to induce separation of the support substrate (25).

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 21/268 - Bombardment with wave or particle radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
• H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
• H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices

Abstract

A process for fabricating a multilayer structure is provided as well as the structure itself. In accordance with one embodiment, the process includes growing a growth layer on a silicon substrate by epitaxial growth, forming at least one pattern from the growth layer, depositing an oxide layer on the silicon substrate, transferring a silicon active layer onto the oxide layer, forming a cavity in the silicon active layer oxide layer above the pattern, and growing a III-V material in the cavity.

IPC Classes  ?

• H01L 31/0328 - Inorganic materials including, apart from doping materials or other impurities, semiconductor materials provided for in two or more of groups

Abstract

The invention provides an improved CVD reactor sub-system including a modular reactor enclosure and function modules. The modular reactor enclosure can accommodate a commercially available cold-wall CVD reactor chamber, and the function modules can be arranged on the reactor enclosure to provide functions necessary to perform a CVD process with the reactor chamber. Preferred function modules include modules for providing heat to a CVD reactor chamber and modules for measuring conditions internal to a CVD reactor chamber. The invention also provides methods for configuring such a CVD reactor sub-system, in particular configuring the sub-system to best perform a particular CVD process, and kits for performing such configuring. Advantageously, the invention allows a single CVD reactor sub-system to be reconfigured and rearranged so that it can best perform a number of different CVD processes.

IPC Classes  ?

• H01L 21/205 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth using reduction or decomposition of a gaseous compound yielding a solid condensate, i.e. chemical deposition

Abstract

A support having a larger density of crystalline defects, an insulating layer disposed on a first region of a front face of the support, and a superficial layer disposed on the insulating layer. An additional layer can be disposed at least on a second region of the front face of the support has a thickness sufficient to bury crystalline defects of the support. A substrate can also include an epitaxial layer arranged at least over the first region of the front face of the support, between the support and the insulation layer. Also, a method of making the substrate by forming a masking layer on the first region of the superficial layer and removing the superficial layer and the insulating layer in the second region uncovered by the masking layer. The additional layer is formed in the second region and then planarized.

IPC Classes  ?

• H01L 27/04 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body

Abstract

The invention concerns a heterojunction bipolar transistor comprising a support, and epitaxially grown from said support, at least: one collecting, respectively emitting, layer; at least one base layer; and at least one emitting, respectively collecting, layer. The collecting, respectively emitting, layer comprises: at least one first undercoat contacted with said base layer, substantially of similar composition as said emitting, respectively collecting, layer; and at least one second undercoat on the side opposite said base layer relative to said first undercoat.

IPC Classes  ?

• H01L 29/66 - Types of semiconductor device
• H01L 21/331 - Transistors

Abstract

In preferred embodiments, this invention provides a semiconductor structure that has a semi-conducting support, an insulating layer arranged on a portion of the support and a semi-conducting superficial layer arranged on the insulating layer. Electronic devices can be formed in the superficial layer and also in the exposed portion of the semi-conducting bulk region of the substrate not covered by the insulating layer. The invention also provides methods of fabricating such semiconductor structures which, starting from a substrate that includes a semi-conducting superficial layer arranged on a continuous insulating layer both of which being arranged on a semi-conducting support, by transforming at least one selected region of a substrate so as to form an exposed semi-conducting bulk region of the substrate.

IPC Classes  ?

• H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
• H01L 21/70 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereofManufacture of integrated circuit devices or of specific parts thereof

Abstract

In one embodiment, the invention provides substrates that are structured so that devices fabricated in a top layer thereof have properties similar to the same devices fabricated in a standard high resistivity substrate. Substrates of the invention include a support having a standard resistivity, a semiconductor layer arranged on the support substrate having a high-resistivity, preferably greater than about 1000 Ohms-cm, an insulating layer arranged on the high-resistivity layer, and a top layer arranged on the insulating layer. The invention also provides methods for manufacturing such substrates.

IPC Classes  ?

• H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth

Abstract

In preferred embodiments, the invention provides substrates that include a support, a first insulating layer arranged on the support, a non-mono-crystalline semi-conducting layer arranged on the first insulating layer, a second insulating layer arranged on the non-mono-crystalline semi-conducting layer; and top layer disposed on the second insulating layer. Additionally, a first gate electrode can be formed on the top layer and a second gate electrode can be formed in the non-mono-crystalline semi-conducting layer. The invention also provides methods for manufacture of such substrates.

IPC Classes  ?

• H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth

Abstract

In order to polish a germanium layer (121), a first step comprising the mechanochemical polishing of the surface (121a) of the germanium layer (121) is carried out with a first polishing solution having an acid pH. The first polishing step is followed by a second mechanochemical polishing step comprising the mechanochemical polishing of the surface of the germanium layer (121), carried out with a second polishing solution having a basic pH.

IPC Classes  ?

• B24B 37/04 - Lapping machines or devicesAccessories designed for working plane surfaces
• H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
• H01L 21/321 - After-treatment

Abstract

The present invention relates to a process for manufacturing a structure comprising a germanium layer (3) on a support substrate (1), characterised in that it comprises the following steps: (a) formation of an intermediate structure (10) comprising said support substrate (1), a silicon oxide layer (20) and said germanium layer (3), the silicon oxide layer (20) being in direct contact with the germanium layer (3), (b) application to said intermediate structure (10) of a heat treatment, in a neutral or reducing atmosphere, at a defined temperature and for a defined time, to diffuse at least part of the oxygen from the silicon oxide layer (20) through the germanium layer (3).

IPC Classes  ?

• H01L 21/762 - Dielectric regions

Abstract

In one embodiment, the invention provides engineered substrates having a support with surface pits, an intermediate layer of amorphous material arranged on the surface of the support so as to at least partially fill the surface pits, and a top layer arranged on the intermediate layer. The invention also provides methods for manufacturing the engineered substrates which deposit an intermediate layer on a pitted surface of a support so as to at least partially fill the surface pits, then anneal the intermediate layer, then assemble a donor substrate with the annealed intermediate layer to form an intermediate structure, and finally reduce the thickness of the donor substrate portion of the intermediate structure in order to form the engineered substrate.

IPC Classes  ?

• H01L 21/70 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereofManufacture of integrated circuit devices or of specific parts thereof

Abstract

In preferred embodiments, the invention provides substrates that include a support, a first insulating layer arranged on the support, a non-mono-crystalline semi-conducting layer arranged on the first insulating layer, a second insulating layer arranged on the non-mono-crystalline semi-conducting layer; and top layer disposed on the second insulating layer. Additionally, a first gate electrode can be formed on the top layer and a second gate electrode can be formed in the non-mono-crystalline semi-conducting layer. The invention also provides methods for manufacture of such substrates.

IPC Classes  ?

• H01L 29/66 - Types of semiconductor device
• H01L 21/30 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups
• H01L 21/46 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups

Abstract

In one embodiment, the invention provides substrates that are structured so that devices fabricated in a top layer thereof have properties similar to the same devices fabricated in a standard high resistivity substrate. Substrates of the invention include a support having a standard resistivity, a semiconductor layer arranged on the support substrate having a high-resistivity, preferably greater than about 1000 Ohms-cm, an insulating layer arranged on the high-resistivity layer, and a top layer arranged on the insulating layer. The invention also provides methods for manufacturing such substrates.

IPC Classes  ?

• H01L 29/02 - Semiconductor bodies

Abstract

A method for forming a device wafer with a recyclable support by providing a wafer having first and second surfaces, with at least the first surface of the wafer comprising a semiconductor material that is suitable for receiving or forming electronic devices thereon, providing a supporting substrate having upper and lower surfaces, and providing the second surface of the wafer or the upper surface of the supporting substrate with void features in an amount sufficient to enable a connecting bond therebetween to form a construct wherein the bond is formed at an interface between the wafer and the substrate and is suitable to maintain the wafer and supporting substrate in association while forming or applying electronic devices to the first surface of the wafer, but which connecting bond is severable at the interface due to the void features to separate the substrate from the wafer so that the substrate can be reused.

IPC Classes  ?

• H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body

Abstract

The invention relates to a method for preparing hydrophobic surfaces which find their application in direct silicon bonding and strained material layer growth. The method comprises providing a substrate and subjecting the substrate to a mixed plasma treatment, wherein the mixed plasma comprises a reducing gas plasma, in particular H2, and an inert gas plasma, in particular Ar and/or He.

IPC Classes  ?

• H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
• H01L 21/762 - Dielectric regions

Abstract

A method of fabricating a device layer structure includes providing a Hi-nitride semiconductor layer which is bonded to a bonding substrate. A device layer structure is formed on a nitrogen polar surface of the Ill-nitride semiconductor layer. The device layer structure includes an indium gallium nitride layer with a metal polar surface adjacent to the nitrogen polar surface of the ID-nitride semiconductor layer.

IPC Classes  ?

• H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials

Abstract

The invention provides methods which can be applied during the epitaxial growth of two or more layers of Group Ill-nitride semiconductor materials so that the qualities of successive layer are successively improved. In preferred embodiments, surface defects interact with a protective layer of a protective material to form amorphous complex regions capable of preventing the further propagation of defects and dislocations. The invention also includes semiconductor structures fabricated by these methods.

IPC Classes  ?

• H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth

Abstract

Method for transferring a thin layer from a lithium-based starting substrate, comprising: a step of proton exchange between this substrate and a first electrolyte, which is an acid, through a free face of this substrate so as to replace lithium ions of the substrate by protons, in a proportion between 10% and 80%, over a depth e1; a step of reverse proton exchange between this substrate and a second electrolyte, through this free face, so as to replace, over a second depth e2 smaller than the first depth e1, at least practically all the protons with lithium ions, so as to leave an intermediate layer between the depths e1 and e2, in which intermediate layer protons incorporated during the proton exchange step are left, the depth e2 defining a thin layer between said free face and the intermediate layer; a heat treatment step carried out under conditions suitable for embrittling the intermediate layer; and a separating step suitable for causing the thin film to separate from the rest of the substrate at the intermediate layer.

IPC Classes  ?

• C30B 31/04 - Diffusion or doping processes for single crystals or homogeneous polycrystalline material with defined structureApparatus therefor by contacting with diffusion materials in the liquid state
• C30B 33/02 - Heat treatment

Abstract

The invention concerns a method of bonding two wafers (20, 30) by molecular bonding in which a first propagation of a bonding wave initiated from a point of pressure (43) applied to at least one (30) of the two wafers is followed by a second propagation of the bonding wave over a zone covering the point of pressure (43). The second bonding wave propagation may be obtained by interposing a separating element (41) between the two wafers and by withdrawing the element at least after the start of the first bonding wave propagation or by partially unbonding the surfaces of the assembled wafers over a zone located in the vicinity of the point of pressure (63).

IPC Classes  ?

• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• H01L 27/146 - Imager structures
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 21/98 - Assembly of devices consisting of solid state components formed in or on a common substrateAssembly of integrated circuit devices

Abstract

The present invention provides a chromium-free etching composition suitable for treating various silicon-containing surfaces, including strained silicon on insulator surfaces as well as stressed silicon surfaces. The novel and inventive etching composition in accordance with the present invention comprises hydrofluoric acid, nitric acid, acetic acid and an alkali iodide, preferably potassium iodide.

IPC Classes  ?

• G01N 1/32 - PolishingEtching

Abstract

In order to reduce and render uniform the surface roughness and variations in thickness of a layer after detachment (post-fracture) of a donor substrate (18), the mean temperature of the donor substrate (18) during implantation thereof is controlled so as to be in the range 20°C to 150°C with a maximum temperature variation of less than 30°C.

IPC Classes  ?

• H01L 21/762 - Dielectric regions

Abstract

The present invention relates to a multilayer wafer structure containing a layer (25) that is lattice compatible with III-V compounds, said layer (25) being in contact with one face of an insulating layer (8), wherein the face of the insulating layer (8) opposite to said layer (25) is in contact with a silicon layer (7) that contains at least one waveguide, wherein the silicon layer (7) and insulating layer (8) contain either or both of: at least one continuous cavity filled with materials such as to constitute a photodetector zone (61), and/or at least one continuous cavity filled with materials such as to constitute a light source zone (62).

IPC Classes  ?

• H01L 21/8258 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using a combination of technologies covered by , , or
• H01L 31/12 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto
• H01L 31/153 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto the light source or sources being controlled by the semiconductor device sensitive to radiation, e.g. image converters, image amplifiers or image storage devices the light sources and the devices sensitive to radiation all being semiconductor devices characterised by at least one potential or surface barrier formed in, or on, a common substrate
• H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
• H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

Abstract

The present invention relates to a method forfabricating a substrate (1) of semiconductor on insulatortype, comprising the following steps: - formation of an oxide layer (20) on a donor substrate (10) or a receiver substrate (30), - implantation of atomic species in the donor substrate so as to form a weakened zone(12), - bonding of the donor substrate onto the receiver substrate (30), the oxide layer (20) being at the bonding interface, - fracturing the donor substrate in the weakened zone (12) and transferring a layer of the donor substrate to the receiver substrate (30), - recycling of the remainder (2) of the donor substrate to form a receiver substrate (40) used for fabrication of a second semiconductor on insulator type 10 substrate. Before the oxidation step, a layer(14) of semiconducting materialis formed by epitaxy onthedonor substrate (10). In the implantation step, the weakened zone (12) formed in said epitaxied layer (14) so that the transferred layer is an epitaxied semiconducting material layer (140). And the donor substrate (10) is chosen comprising oxygen precipitates with a density of less than1010 /cm3 and/or a mean size of less than 500 nm.

IPC Classes  ?

• H01L 21/762 - Dielectric regions

Abstract

The invention relates to a substrate comprising successively a base wafer (1), an insulating layer (2) and a top semiconductor layer (3), characterised in that the insulating layer (2) comprises at least a zone wherein the density of charges is in absolute value higher than 1010 charges/cm2. The invention also relates to a process for making such a substrate.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Abstract

The present invention employs a semiconductor growth system which includes a reaction chamber and a reactor component which is a single piece of boron carbide. The reaction chamber is typically a Ill-nitride reaction chamber and the reactor component is positioned within it. The reactor component can be of many different types, such as a susceptor control ring, susceptor and wafer holder.

IPC Classes  ?

• C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
• C30B 25/12 - Substrate holders or susceptors
• H01J 37/32 - Gas-filled discharge tubes

Abstract

The invention relates to a method for fabricating a semiconductor substrate comprising the steps of: providing a silicon on insulator type substrate comprising a base, an insulating layer and a first semiconductor layer, doping the first semiconductor layer to thereby obtain a modified first semiconductor layer, and providing a second semiconductor layer with a different dopant concentration than the modified first semiconductor layer over, in particular on, the modified first semiconductor layer. With this method, an improved dopant concentration profile can be achieved through the various layers which makes the substrates in particular suitable for optoelectronic applications.

IPC Classes  ?

• H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
• H01L 27/146 - Imager structures

Abstract

The present invention relates to the field of semiconductor processing and provides apparatus and methods that improve chemical vapor deposition (CVD) of semiconductor materials by promoting more efficient thermalization of precursor gases prior to their reaction. In preferred embodiments, the invention comprises heat transfer structures and their arrangement within a CVD reactor so as to promote heat transfer to flowing process gases. In certain preferred embodiments applicable to CVD reactors transparent to radiation from heat lamps, the invention comprises radiation-absorbent surfaces placed to intercept radiation from the heat lamps and to transfer it to flowing process gases.

IPC Classes  ?

• C23C 16/30 - Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
• C23C 16/448 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for generating reactive gas streams, e.g. by evaporation or sublimation of precursor materials

Abstract

The present invention relates to a method for transferring a layer (12) by the formation of an embhttlement area in a source substrate (10) onto a support substrate (30), comprising the successive steps of: (a) formation of a bonding layer (20) on the source substrate (10), (b) implantation of ions from a first species in the source substrate (10) through the bonding layer (20), so as to form an embrittlement area defining the layer (12) to transfer, (c) placement of the bonding layer (20) and the support substrate (30) in close contact, (d) fracturing of the source substrate (10) along the embrittlement area so as to transfer the layer (12) onto the support substrate (30). Said method comprises, before step (a), the implantation of ions from a second species in the source substrate (10) so as to form said embrittlement area.

IPC Classes  ?

• H01L 21/762 - Dielectric regions

Abstract

The present invention relates to a method for reducing the amount or eliminating the crystalline defects in a semiconductor layer of a composite structure, said composite structure comprising said semiconductor layer bonded to a handle substrate, the method comprising providing a handle substrate, providing said semiconductor layer, bonding said handle substrate to the said semiconductor layer, in order to obtain a bonded composite structure, the method being characterized in that the semiconductor layer is selected to have a thickness greater than a threshold value which is representative of the size of the crystalline defects, and further comprises a heat treatment of said bonded composite structure with a high temperature and a duration selected for reducing the amount or eliminating the crystalline defects.

IPC Classes  ?

• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
• H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Abstract

13 Abstract Method for manufacturing a SeOI substrate (1) with a thin buried oxide, said substrate comprising: -a thin working layer (11) made from one or more semiconductor material(s); -a support layer; and -a thin buried oxide layer (12) between the working layer and the support layer; said method comprising: -a manufacturing step of an intermediate SeOI substrate having a buried oxide layer with a thickness greater than a thickness desired for said thin buried oxide layer; -a dissolution step of said buried oxide layer (12) in order to form therewith said thin buried oxide layer; characterized in that the method comprises after said dissolution step an oxidation step of said substrate for creating an oxidized layer (13) on the substrate, and an oxide migration step for diffusing at least a part of said oxide layer through the working layer, in order to increase the electrical interface quality of said substrate and decrease its Dit value.

IPC Classes  ?

• H01L 21/762 - Dielectric regions

Abstract

The invention relates to a method for preparing a surface of a semiconductor substrate comprising the steps of oxidizing the surface of the semiconductor substrate to thereby transform the natural oxide into an artificial oxide and of removing the artificial oxide, in particular to obtain an oxide-free substrate surface.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
• H01L 21/762 - Dielectric regions

Abstract

The invention relates to a method for bonding two substrates, in particular two semiconductor substrates which, in order to be able to improve the reliability of the process, provides the step of providing a gaseous flow over the bonding surfaces of the substrates The invention also relates to a corresponding bonding equipment

IPC Classes  ?

• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• H01L 21/762 - Dielectric regions

Abstract

The invention relates to a method for manufacturing heterostructures for applications in the fields of electronics, optics or opto-electronics. This method is remarkable in that it consists of : - forming and/or depositing a silicon oxide Siθ2 layer (3, 4) with a thickness of less than or equal to 25 nanometers on a donor substrate (1) and/or on a receiver substrate (2), - submitting this or these substrates (1, 2) to a treatment at a temperature comprised between 900°C and 1,200°C, under an atmosphere containing at least argon and/or hydrogen and no oxygen, in order to form in said silicon oxide layer (3, 4), trapping holes (30, 40), - bonding both substrates (1, 2), - carrying out annealing for reinforcing the bonding interface (5) at low temperature, said trapping holes (30, 40) being capable of retaining the gas species present at this interface, - transferring a portion (14) of the donor substrate (1), onto the receiver substrate (2).

IPC Classes  ?

• H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
• H01L 21/762 - Dielectric regions

Abstract

The invention concerns a method of fabricating a composite structure (14) comprising at least one thin film (4) bonded to a support substrate (10), a bonding layer of oxide (12) being formed by deposition between the support substrate (10) and the thin film (4). The thin film and the support substrate have a mean thermal expansion coefficient of 7 X 10-6 K-1 or more. The bonding layer of oxide (12) is formed by low pressure chemical vapor deposition (LPCVD) of a layer of oxide on the bonding face of the support substrate (10) and/or on the bonding face of the thin film (4). The thin film has a thickness of 5 micrometers or less while the thickness of the layer of oxide (12) is equal to or greater than the thickness of the thin film (4).

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth

Abstract

The invention relates to a method of fabricating materials by epitaxy, comprising a step of epitaxial growth of at least one layer (15) of a material on a composite structure (14). The composite structure comprises at least one thin film (4) bonded to a support substrate (10), a bonding layer (25) being formed by deposition between the support substrate (10) and the thin film (4), the thin film (4) and the support substrate (10) having a mean thermal expansion coefficient of 7 x 10-6 K-1 or more. The bonding layer of oxide (25) is formed by low pressure chemical vapor deposition (LPCVD) of a layer of oxide of silicon on the bonding face of the support substrate (10) and/or on the bonding face of the thin film (4). The thickness of the thin film (4) is less than or equal to the thickness of the oxide layer. The method also includes a heat treatment carried out at a temperature that is higher than the temperature for deposition of the layer of oxide of silicon and for a predetermined period.

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
• H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping