Abstract

The invention relates to a method for manufacturing a composite structure comprising a thin layer of monocrystalline material arranged on a carrier substrate made of polycrystalline material, the manufacturing method comprising the following steps: a) providing a raw disk made of polycrystalline material having two faces; b) measuring at least one curvature parameter of the raw disk so as to define a first face with a convex profile and a second face with a concave profile, and selecting the first face to correspond to a front face of the carrier substrate at the end of step c); c) preparing the carrier substrate from the raw disk, involving mechanical and/or chemical treatment of the faces of the raw disk, the carrier substrate having a front face and a rear face corresponding to the first face and the second face of the raw disk, respectively; d) transferring the thin layer onto the front face of the carrier substrate in order to obtain the composite structure.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting

Abstract

The invention relates to a method for manufacturing a composite structure comprising a thin layer of monocrystalline material arranged on a carrier substrate, the manufacturing method comprising the following steps: a) providing a wafer having two faces and originating from a raw disk that has been mechanically ground by removing a thickness of 100 micrometers or less from both faces of the raw disk; b) preparing the carrier substrate from the wafer, involving mechanical and/or chemical treatment of both faces of the wafer; the carrier substrate having two faces; c) measuring at least one curvature parameter of the wafer or of the carrier substrate, and selecting: - from between the two faces of the wafer, the face having a negative arc, such that it corresponds to a front face of the carrier substrate at the end of step b); or - from between the two faces of the carrier substrate, the face having a negative arc, such that it corresponds to a front face of the carrier substrate; d) transferring the thin layer onto the front face of the carrier substrate in order to obtain the composite structure.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting

Abstract

CarDonDonCarDonDonDon) consisting of at least 99.92% of silicon isotope 28Si.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/762 - Dielectric regions

Abstract

The invention relates to a method for preparing a single-domain thin film made of ferroelectric material, the method comprising transferring the layer from a donor substrate to a receiver substrate, followed by a heat treatment (Stab) and then thinning (Thin), the heat treatment comprising: increasing the temperature to a high temperature of between 400°C and the Curie temperature of the ferroelectric material forming the layer; maintaining the temperature for a time of 30 min or more; then lowering the temperature, wherein the temperature increase is carried out by a temperature ramp at a heating rate greater than 7°C/min, such that the transferred ferroelectric layer reaches a temperature between 400°C and the Curie temperature at the end of the ramp.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• H10N 30/072 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
• H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Abstract

The invention relates to a treatment method applied to a plurality of substrates (Sub) kept parallel to one another, the treatment comprising at least two successive sequences of treatments, each of the sequences comprising at least one dipping in at least one chemical bath contained in a container provided with a manifold for injecting a treatment solution, the injection manifold comprising dispensing nozzles, the nozzles being distributed along the injection manifold, each of the substrates (Sub) being arranged substantially perpendicular to the injection manifold, in which method: a first of the at least two dipping operations is carried out with the substrates (Sub) oriented in a first orientation (Or1) that is determined at an angle about an axis normal to the substrates; and a second of the at least two dipping operations is carried out with at least a portion of the substrates oriented in a second orientation (Or2) that is different to the first orientation (Or1).

IPC Classes  ?

• H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
• H01L 21/673 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components using specially adapted carriers

Abstract

The invention relates to a method for preparing a substrate comprising a thin layer (3) of piezoelectric material transferred to a carrier (5), the method being based on Smart Cut technology and comprising a step (S2) of implanting a donor substrate (1) and a joining step (S4). According to the invention, the preparation method comprises, before the implantation step (S2), a plasma treatment step (Sp) that comprises exposing the donor substrate (1) to a neutral gas plasma.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/762 - Dielectric regions
• H10N 30/072 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies

Abstract

The invention relates to a method for producing a composite structure, the method comprising the following steps: a) providing a composite substrate including a carrier substrate and a seed layer of single-crystal III-V material arranged on the carrier substrate via a bonding interface, the carrier substrate having a thermal expansion coefficient different from that of the seed layer, and the seed layer having an intrinsic lattice parameter; b) epitaxially growing a stack of single-crystal III-V layers, referred to as epitaxial layers, on the seed layer, each epitaxial layer having an intrinsic lattice parameter. When the thermal expansion coefficient of the carrier substrate is less than that of the seed layer, at least one epitaxial layer of the stack has a composition selected such that the intrinsic lattice parameter thereof is reduced by 200 ppm to 3000 ppm relative to the intrinsic lattice parameter of the seed layer. When the thermal expansion coefficient of the carrier substrate is greater than that of the seed layer, at least one epitaxial layer of the stack has a composition selected such that the intrinsic lattice parameter thereof is increased by 200 ppm to 3000 ppm relative to the intrinsic lattice parameter of the seed layer. The invention also relates to a composite structure.

IPC Classes  ?

• H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth

Abstract

The invention relates to a method for manufacturing a donor wafer, comprising the following steps: a) providing a donor substrate made of a monocrystalline material, said donor substrate having been recycled at least once, after a transfer of a thin layer of said donor substrate onto a receiver substrate so as to form a composite structure, said composite structure comprising a surface layer formed entirely or partially by the thin layer and arranged on the receiver substrate, and providing the composite structure, b) checking the quality of the composite structure, by inspecting a free surface of the surface layer, to detect defects present on and/or in the surface layer, said defects then being classified as belonging to a first category, considered to be non-critical, or as belonging to a second category, considered to be critical, c) selecting the donor substrate if a density of defects classified as belonging to the second category during step b) is less than a predetermined density, d) assembling the donor substrate selected in step c) on a support substrate, by bonding, to form the donor wafer. The invention also relates to a donor wafer comprising a donor substrate made of monocrystalline silicon carbide, having a thickness of between 100 μm and 300 μm, arranged on a support substrate, and characterized in that a free face of the donor substrate has less than 0.5 defect/cm2 of the micro-hole or inclusion type.

IPC Classes  ?

• H01L 21/66 - Testing or measuring during manufacture or treatment
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

Abstract

The invention relates to a photonic substrate (1) comprising a support (5) having a first face and a second face opposite the first face, an electrical charge trapping layer (4) arranged on the first face of the support (5), a dielectric layer (3; 3a, 3b) arranged on, and in contact with, the electrical charge trapping layer, and an electro-optical layer (2) made of an optical-quality monocrystalline material, the electro-optical layer (2) being arranged on, and in contact with, the dielectric layer (3; 3a, 3b). The invention also relates to an optical device using a substrate of this kind, and to a process for manufacturing said substrate.

IPC Classes  ?

• G02F 1/035 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour based on ceramics or electro-optical crystals, e.g. exhibiting Pockels or Kerr effect in an optical waveguide structure
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

The invention relates to a method for manufacturing an acceptor substrate in order to form a composite substrate, the method comprising a step of providing a base substrate, and a step of depositing, in a deposition chamber, an electric charge trapping layer in contact with the base substrate. The trapping layer comprises from 40% to 80% of silicon atoms, from 0.1% to 45% of oxygen atoms, and from 0.2% to 50% of nitrogen atoms. The step of depositing the trapping layer implements a mixture of precursor gases. The mixture comprises a gas comprising silicon, a gas comprising oxygen and a gas comprising nitrogen. The gas comprising nitrogen is ammonia or a set of molecules that form ammonia in the deposition chamber during the deposition step.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/762 - Dielectric regions

Abstract

32lLTOLTOSiO2SiO2SiO2 being the thickness of the dielectric layer. The invention also relates to a production method.

IPC Classes  ?

• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elementsElectromechanical resonators Details

Abstract

The invention relates to an elastic wave device in the field of elastic wave-based components for fields such as telecommunications. The device of the invention comprises a first electromechanical device, in particular a transducer (3) and a second electromechanical device, in particular a transducer (5), an array of at least one electrode (4000) located between the first transducer (3) and the second transducer (5) in the direction of propagation of the elastic waves, of which array at least one electrode is connected to a predetermined electrical potential (1005, 2005, 3005) via a modifiable impedance (1003, 2003, 3003), and a control means (1007, 2007, 3007) for modifying the modifiable impedance (1003, 2003, 3003).

IPC Classes  ?

• H03H 9/64 - Filters using surface acoustic waves
• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elementsElectromechanical resonators Details
• H03H 9/145 - Driving means, e.g. electrodes, coils for networks using surface acoustic waves

Abstract

32lLNOLNOSiO2SiO2LNOSiO2LNOSiO2SiO2 is equal to between 0.75 and 0.85, preferably between 0.79 and 0.81.

IPC Classes  ?

• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elementsElectromechanical resonators Details

Abstract

32lLTOLTOSiO2SiO2SiO2 being the thickness of the dielectric layer.

IPC Classes  ?

• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elementsElectromechanical resonators Details
• H03H 3/02 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks

Abstract

A semiconductor structure (1) comprising: − a Silicon-On-Insulator substrate (100) comprising: o a base layer (103) comprising silicon; o an intermediate layer (102) on top of the base layer; and o a first silicon layer (101) on top of the intermediate layer (102), the first silicon layer (101) having a (1,0,0) lattice orientation; − a second silicon layer (200) on top of the first silicon layer (101), the second silicon layer (200) having a (1,1,1) lattice orientation; and − an interface layer (300) between the first silicon layer (101) and the second silicon layer (200).

IPC Classes  ?

• H01L 21/762 - Dielectric regions

Abstract

The invention relates to a method for measuring at least one thickness parameter of a superficial layer of an SOI substrate, comprising the following steps: a) measurement of thickness at a predefined number of first points, spatially distributed over the surface, resulting in a first series of values comprising a first maximum and a first minimum, the measurement of thickness being carried out using a first technique; b) production of a complete map of the surface of the superficial layer using a second technique, different from the first technique, the map expressing a physical characteristic of the superficial layer correlated with its thickness; c) analysis of the map so as to identify whether there is a signature liable to be indicative of a thickness variation greater than or equal to the difference between the first maximum and the first minimum, in a localized region of the superficial layer; d) if a signature is identified, measurement of thickness at a plurality of second points positioned in the localized region, resulting in a second series of values comprising a second maximum and/or a second minimum; the measurement of thickness being carried out using the first technique; and e) calculation of at least one thickness parameter, based on the first series of values, and potentially on the second series of values.

IPC Classes  ?

• G01B 11/06 - Measuring arrangements characterised by the use of optical techniques for measuring length, width, or thickness for measuring thickness
• H01L 21/66 - Testing or measuring during manufacture or treatment

Abstract

The invention relates to a method for preparing a composite structure, comprising the following steps: 1) providing a composite structure comprising a growth layer made of monocrystalline silicon carbide, a free face of which extends along a main plane, which growth layer is arranged on a support substrate, the growth layer being delimited by a peripheral perimeter and having a crystallographic orientation such that there is: a disorientation angle between a given crystallographic plane and the free face, a disorientation direction, which corresponds to a projection of an axis normal to the free face onto the crystallographic plane, and a reference direction, which corresponds to a projection of the disorientation direction onto the main plane; 2) forming a trench in the growth layer, the trench having an inner edge which extends at a distance and continuously along the peripheral perimeter, following a contour such that, by defining four cardinal points (North-South-West-East) on the peripheral perimeter, with the West-East direction corresponding to the reference direction: the contour passing through the cardinal points North-West-South follows the general shape of the peripheral perimeter, and the contour passing through the cardinal points North-East-South has a saw-toothed pattern. The invention also relates to a composite structure capable of being made using the aforementioned preparation method.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth

Abstract

The invention relates to a composite structure having a front face and a rear face extending parallel to a main plane, which structure comprises: - a useful layer of single-crystal silicon carbide, a free face of which constitutes the front face, which layer has a first concentration of N-type dopants; - a carrier substrate made of polycrystalline silicon carbide, a free face of which constitutes the rear face, which substrate has a second concentration of N-type dopants, the second concentration being higher than the first concentration; - an intermediate region extending along the main plane and including an interface zone between an assembled face of the useful layer and an assembled face of the carrier substrate; the composite structure being characterised in that the intermediate region comprises inclusions of single-crystal silicon carbide in direct contact with the useful layer and extending, in a direction normal to the main plane, between grains of the carrier substrate, the inclusions having a third concentration of N-type dopants which is between the first concentration and the second concentration. The invention also relates to a method for producing such a composite structure.

IPC Classes  ?

• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials

Abstract

The present invention relates to a method for treating a substrate (10) having a rear face (204) made of polycrystalline silicon carbide and a front face (203) intended for the manufacture of an electronic component, which method comprises: forming a vitreous carbon layer (40) on the rear face (204); transferring a layer (20) made of a monocrystalline semiconductor material onto the front face (203); and, heat treating the substrate after the formation of the carbon layer (40), the carbon layer (40) limiting the increase in the roughness of the rear face (204) during the heat treatment.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
• H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

Abstract

sublaylay) joined to the support assembly (Sprt.Set) so as to obtain a structure (Struct), the ferroelectric layer having a negative polarisation (P1); performing an additional full-field hydrogen implantation step, parameterised so as to correct or prevent the occurrence of polarisation inversion in the volume of the ferroelectric layer and/or at its interface with the support assembly (Sprt.Ens); and applying at least one first heat treatment to the structure (Strct).

IPC Classes  ?

• H10N 30/04 - Treatments to modify a piezoelectric or electrostrictive property, e.g. polarisation characteristics, vibration characteristics or mode tuning
• H10N 30/073 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives

Abstract

The invention comprises: a starting structure (Struct_0) designed to undergo separation by laser irradiation, comprising a substrate (Sub2), a transferred layer (TrLay), and a graphene oxide layer (GO, GO2) interposed between the substrate (Sub2) and the transferred layer (TrLay).

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• H01L 21/268 - Bombardment with wave or particle radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation

Abstract

The present invention relates to a method for treating a substrate having a free surface made of a semiconductor material, in particular a single–crystal semiconductor material, comprising a method for stabilising the surface against the formation of terraces and/or beads, the method comprising: • forming a vitreous carbon layer (30) by a gas-phase carbon reaction on the surface at a temperature (T1) greater than 700°C, preferably greater than 800°C, and strictly lower than 1000°C, preferably lower than 950°C, and more preferably lower than 900°C; and • applying a heat treatment to the substrate after stabilising the surface, wherein the vitreous carbon layer (30) limits the reorganisation of the surface made of a semiconductor material in the form of terraces, the depositing of the carbon layer (30) and the heat treatment being carried out in the same furnace.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
• H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

Abstract

lay-138lay4242laylay) of the starting composite structure (StartStruct).

IPC Classes  ?

• H10N 30/04 - Treatments to modify a piezoelectric or electrostrictive property, e.g. polarisation characteristics, vibration characteristics or mode tuning
• H10N 30/073 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives

Abstract

The present invention relates to a method of method of manufacturing a heterostructure for the manufacture of a Piezoelectric on Insulator, POI, structure, comprising providing a support substrate, forming a block of a piezoelectric material on or over the support substrate, removing a first peripheral portion of the block of a piezoelectric material and a first peripheral portion of the support substrate to obtain an exposed portion of the support substrate with a roughness with a root-mean-square height, Sq, in the range of 0.4 µm to 0.8 µm, thinning the block of a piezoelectric material after removal of the first peripheral portion of the block of a piezoelectric material to obtain a piezoelectric substrate.

IPC Classes  ?

• H10N 30/073 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
• H10N 30/072 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
• H10N 30/086 - Shaping or machining of piezoelectric or electrostrictive bodies by machining by polishing or grinding
• H10N 30/80 - Constructional details

Abstract

The invention relates to a method (100) for polishing a planar substrate (Waf) using a planarising and polishing machine comprising a support plate (Pl) provided with a polishing pad (Pol.Pad), a conditioning head (Cond.Head) for conditioning the polishing pad, and a head (Pol.Head) for holding the planar substrate (Waf) against the polishing pad, the method comprising a first step (110) of a first conditioning of the polishing pad (Pol.Pad) using the conditioning head (Cond.Head), wherein the planar substrate (Waf) is not subjected to any polishing operation; a second step (120) of a first polishing of the planar substrate (Waf), wherein the polishing pad is not subjected to any conditioning operation; and a third step (130) in which (i) a second polishing of the planar substrate (Waf) is performed and, simultaneously, (ii) a second conditioning of the polishing pad (Pol.Pad) is performed.

IPC Classes  ?

• B24B 53/017 - Devices or means for dressing, cleaning or otherwise conditioning lapping tools
• B24B 37/04 - Lapping machines or devicesAccessories designed for working plane surfaces

Abstract

The invention relates to a semiconductor substrate (Sub) configured to allow laser separation of a layer of active material (ActMat), comprising: a support substrate (Sprt); an inorganic layer (Inorg) on the support substrate, wherein the inorganic layer is formed of a material selected from among Al2O3, TiO2, WO3, La2O3, LaAlO3 and TiN; an electrically insulating layer (Ins) on the inorganic layer; and the layer of active material (ActMat) on the electrically insulating layer, wherein the layer of active material is monocrystalline.

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/268 - Bombardment with wave or particle radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation

Abstract

The invention relates to a method for assembling two substrates by molecular adhesion, at least one of the two substrates being provided with a dielectric surface layer. The method comprises activating the dielectric surface layer by exposure to a plasma formed between two electrodes (4a, 4b) of an activation chamber (3), for an activation period of 15 seconds to 2 minutes and during which a radiofrequency power is applied to one of the electrodes. The method comprises injecting into the activation chamber (3) a controlled flow of oxygen or nitrogen and a controlled flow of a gas comprising sulphur. The method is characterised in that the radiofrequency power has a density strictly greater than 1.1 W/cm^2.

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials

Abstract

The invention relates to a method for manufacturing a tiled donor substrate, the method comprising the following steps: a) providing an initial structure comprising a carrier substrate having a front face and a rear face, and a plurality of tiles made of a first monocrystalline material, wherein the tiles are arranged on the front face and are spaced apart from one another; b) forming a complementary layer by means of an additive manufacturing technique, wherein the complementary layer: - is arranged between the tiles, in contact with the front face of the carrier substrate; - is composed of a material, referred to as the second material, having a coefficient of thermal expansion matched to that of the first material; c) applying a mechanical and/or chemical-mechanical surface treatment to the complementary layer and to the tiles, in order to obtain the tiled donor substrate, wherein a front face of the substrate has a flat and continuous surface at which the plurality of tiles and the complementary layer are flush.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials

Abstract

The invention relates to a method for preparing a support substrate made of polycrystalline material, the preparation method comprising the following steps: a) providing a raw disc made of polycrystalline material, having two faces; b) rough grinding of at least one of the faces of the raw disc, with a grinding wheel, the abrasive grit of which has an average size greater than or equal to 10 μm, to obtain a surface-ground disc having at least one surface-ground face; c) applying a heat treatment to the surface-ground disc, at a temperature above a growth temperature of the raw disc employed in step a), and below a melting temperature of the polycrystalline material, so as to obtain an annealed disc, d) thinning the annealed disc, from the at least one surface-ground face, said thinning including fine grinding with a grinding wheel, the abrasive grit of which has an average size of less than 10 μm, so as to obtain the support substrate.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting

Abstract

The invention relates to a method for preparing a support substrate made of polycrystalline material, the preparation method comprising the following steps: a) providing a raw disc made of polycrystalline material, having two faces; b) rough grinding of at least one of the faces of the raw disk in order to obtain a surface-ground disc having at least one surface-ground face, the rough grinding leading to the formation of a damaged superficial region on said surface-ground face; the damaged superficial region comprising a work-hardened superficial layer and a stressed underlying layer; c) applying a heat treatment to the surface-ground disc, the temperature and the duration of the heat treatment being defined so as to relax the stresses present in the stressed layer; step c) leading to the obtaining of an annealed disc comprising, at the at least one surface-ground face, a superficial first annealed layer, instead of the work-hardened layer, and an underlying second annealed layer, instead of the stressed layer; d) thinning the annealed disc, from the at least one surface-ground face, in order to remove the first annealed layer; step d) leading to the obtaining of the support substrate in which all or part of the second annealed layer is preserved.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting

Abstract

The invention relates to a method for transferring a thin film (7) onto a final carrier (11), the thin film (7) and the final carrier (11) having different coefficients of thermal expansion. The method comprises transferring the thin film (7) onto an intermediate carrier (5) at a first bonding interface (IA1) and forming a dielectric surface layer (10) on the exposed face of the thin film (7). The method further comprises activating the dielectric surface layer (10) by exposing it to a plasma having a radiofrequency power density of strictly greater than 1.1 W/cm^2, then assembling the thin film (7) via the dielectric surface layer (10) to the final carrier (11) and thus defining a second bonding interface (IA2). Finally, the method comprises mechanically stressing the final carrier (11) and/or the intermediate carrier (5) to remove the intermediate carrier (5) from the thin layer (7) at the first bonding interface (IA1).

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials

Abstract

The invention relates to a method for manufacturing a substrate, according to which an adhesive layer (115) sandwiched between a handling substrate (100) and a piezoelectric substrate (101) is polymerised at a polymerisation site, and, after the polymerisation step, the heterostructure (107) is moved to another site. The method is characterised in that, during the polymerisation step, the heterostructure (107) is colder than an ambient temperature of the other site. The invention also relates to a substrate (119) comprising an adhesive layer (115) sandwiched between a handling substrate (100) and a piezoelectric substrate (101), characterised in that, when the substrate (119) has a temperature between 20°C and 25°C, in particular between 20°C and 22°C, the adhesive layer (115) is under compression, in particular with respect to the handling substrate (100) in such a way as to induce a curve (BOW) of the substrate.

IPC Classes  ?

• H10N 30/073 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives

Abstract

The invention relates to a method for producing a stacked structure comprising a layer of semiconductor material bonded to a substrate, which comprises: producing a heterostructure by: • forming an intermediate layer made of a two-dimensional material on a growth substrate (1); patterning the intermediate layer with a plurality of openings to form a patterned intermediate layer (3); growing a semiconductor material on the patterned intermediate layer (3) by epitaxial lateral overgrowth to form a continuous epitaxial layer (4) on the patterned intermediate layer; forming a first assembly by bonding the heterostructure to a handling substrate (6), the continuous epitaxial layer being located at the bonding interface; separating the first assembly at the patterned intermediate layer (3) so as to obtain a second assembly resulting from transferring the continuous epitaxial layer (4) from the heterostructure to the handling substrate (6).

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• H01L 21/762 - Dielectric regions

Abstract

The invention relates to a method for preparing a carrier (1) for a composite substrate (S), which method comprises forming a superficial porous layer (P) on a first face (1c) of the carrier (1), and dispensing a viscous solution comprising a solvent and a precursor of a filler material on the first face (1c) of the carrier (1) so as to absorb at least some of the viscous solution in open pores of the superficial porous layer (P). In a fourth step, the carrier (1) is heat-treated to transform the viscous solution present in the open pores in order to fill the open pores with the filler material.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/762 - Dielectric regions

Abstract

The invention relates to a method for direct bonding between two substrates, the method comprising the following steps: (a) providing a first substrate and a second substrate respectively comprising a first bonding surface made of hydrophilic silicon oxide and a second bonding surface made of hydrophilic silicon oxide; (b) depositing a specific compound on the first bonding surface made of hydrophilic silicon oxide, the specific compound being an organic compound consisting of a basic functional group and substituents of the basic functional group, each substituent being a hydrophobic group; (c) bringing the first bonding surface made of hydrophilic silicon oxide, on which the specific compound has been deposited, into contact with the second bonding surface made of hydrophilic silicon oxide, so as to adhere the first substrate to the second substrate.

IPC Classes  ?

• C09J 5/00 - Adhesive processes in generalAdhesive processes not provided for elsewhere, e.g. relating to primers
• C09J 5/02 - Adhesive processes in generalAdhesive processes not provided for elsewhere, e.g. relating to primers involving pretreatment of the surfaces to be joined
• C09J 5/06 - Adhesive processes in generalAdhesive processes not provided for elsewhere, e.g. relating to primers involving heating of the applied adhesive
• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• H01L 21/3105 - After-treatment
• H01L 21/762 - Dielectric regions
• H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth

Abstract

The invention relates to a method for directly bonding two substrates, the method comprising the following steps: (a) providing a first substrate and a second substrate respectively comprising a first hydrophilic silicon oxide bonding surface and a second hydrophilic silicon oxide bonding surface; (b) depositing a specific compound on the first hydrophilic silicon oxide bonding surface, the specific compound being derived from the ammonia molecule or the ammonium ion by at least the substitution of a hydrogen atom with a hydroxyl -OH group and/or an amino -NH2 group, the specific compound not comprising carbon atoms; and (c) bringing the first hydrophilic silicon oxide bonding surface on which the specific compound has been deposited into contact with the second hydrophilic silicon oxide bonding surface, so that the first substrate is adhered to the second substrate.

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

The invention relates to a method for directly bonding two substrates, the method comprising the following steps: a) providing a first substrate and a second substrate comprising, respectively, a first bonding surface made of hydrophilic silicon oxide and a second bonding surface made of hydrophilic silicon oxide, b) adding fluoride ions to the first hydrophilic silicon oxide bonding surface; c) bringing the first hydrophilic silicon oxide bonding surface into contact with the second hydrophilic silicon oxide bonding surface, so that the first substrate is adhered to the second substrate, by way of the fluoride ions at the bonding interface.

IPC Classes  ?

• H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
• H01L 21/762 - Dielectric regions
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

The present invention relates to an elastic-wave device, in particular a shear-wave device, comprising a piezoelectric material (3), in particular a ferroelectric material with first domains (3a) of a first polarization direction (13a) and second domains (3b) with a second polarization direction (13b), the first direction (13a) being opposite to the second direction, wherein the first and second domains (3a, 3b) are alternated periodically in a direction d, referred to as the periodic direction, perpendicular to the normal n of the surface of the piezoelectric material (3), and a pair of interdigitated comb electrodes (15a, 15b) buried in the piezoelectric material (3) having respective comb teeth (17a1 to 17a3 and 17b1 to 17b3) extending essentially perpendicular to the periodic direction d and to the normal n.

IPC Classes  ?

• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elementsElectromechanical resonators Details
• H03H 3/10 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves for obtaining desired frequency or temperature coefficient
• H03H 9/64 - Filters using surface acoustic waves
• H10N 30/045 - Treatments to modify a piezoelectric or electrostrictive property, e.g. polarisation characteristics, vibration characteristics or mode tuning by polarising

Abstract

The present invention relates to an elastic wave device, in particular a shear wave device, comprising a piezoelectric material (3), in particular a ferroelectric material with first domains (3a) having a first polarisation direction (13a) and second domains (3b) having a second polarisation direction (13b), wherein the first direction (13a) is opposite to the second direction, and wherein the first and second domains (3a, 3b) alternate periodically in a direction d, referred to as the periodic direction, which is perpendicular to the normal n of the surface of the piezoelectric material (3), and a pair of interdigitated comb electrodes (15a, 15b) above, in particular on, the piezoelectric material (3), the respective comb teeth (17al to 17a3 and 17bl to 17b3) of which extend essentially perpendicular to the periodic direction d and to the normal n of the substrate surface.

IPC Classes  ?

• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elementsElectromechanical resonators Details
• H03H 3/10 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves for obtaining desired frequency or temperature coefficient
• H03H 9/64 - Filters using surface acoustic waves
• H10N 30/045 - Treatments to modify a piezoelectric or electrostrictive property, e.g. polarisation characteristics, vibration characteristics or mode tuning by polarising

Abstract

The present invention relates to an elastic-wave device, in particular a shear-wave device, comprising a piezoelectric material (3), in particular a ferroelectric material with first domains (3a) of a first polarization direction (13a) and second domains (3b) with a second polarization direction (13b), the first direction (13a) being opposite to the second direction, wherein the first and second domains (3a, 3b) are alternated periodically in a direction d, referred to as the periodic direction, perpendicular to the normal n of the surface of the piezoelectric material (3), and a pair of interdigitated comb electrodes (15a, 15b) buried in the piezoelectric material (3) having respective comb teeth (17a1 to 17a3 and 17b1 to 17b3) extending essentially perpendicular to the periodic direction d and to the normal n.

IPC Classes  ?

• H03H 3/10 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves for obtaining desired frequency or temperature coefficient
• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elementsElectromechanical resonators Details
• H03H 9/64 - Filters using surface acoustic waves
• H10N 30/045 - Treatments to modify a piezoelectric or electrostrictive property, e.g. polarisation characteristics, vibration characteristics or mode tuning by polarising

Abstract

The present invention relates to an elastic-wave device, in particular a shear-wave device, comprising a piezoelectric material (3), in particular a ferroelectric material with first domains (3a) of a first polarization direction (13a) and second domains (3b) with a second polarization direction (13b), the first direction (13a) being opposite to the second direction, wherein the first and second domains (3a, 3b) are alternated periodically in a direction d, referred to as the periodic direction, perpendicular to the normal n of the surface of the piezoelectric material (3), and a pair of interdigitated comb electrodes (15a, 15b) buried in the piezoelectric material (3) having respective comb teeth (17a1 to 17a3 and 17b1 to 17b3) extending essentially perpendicular to the periodic direction d and to the normal n.

IPC Classes  ?

• H03H 3/10 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves for obtaining desired frequency or temperature coefficient
• H03H 9/64 - Filters using surface acoustic waves
• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elementsElectromechanical resonators Details
• H10N 30/045 - Treatments to modify a piezoelectric or electrostrictive property, e.g. polarisation characteristics, vibration characteristics or mode tuning by polarising

Abstract

The present invention relates to an elastic wave device, in particular a shear wave device, comprising a piezoelectric material (3), in particular a ferroelectric material with first domains (3a) having a first polarisation direction (13a) and second domains (3b) having a second polarisation direction (13b), the first direction (13a) being opposite to the second direction, wherein the first and second domains (3a, 3b) alternate periodically in a direction d, referred to as the periodic direction, which is perpendicular to the normal n to the surface of the piezoelectric material (3), and a pair of interdigitated comb electrodes (15a, 15b) above, in particular on, the piezoelectric material (3), the respective comb teeth (17a1 to 17a3 and 17b1 to 17b3) of which extend essentially perpendicular to the periodic direction d and to the normal n to the surface of the substrate.

IPC Classes  ?

• H03H 3/10 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves for obtaining desired frequency or temperature coefficient
• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elementsElectromechanical resonators Details
• H03H 9/64 - Filters using surface acoustic waves
• H10N 30/045 - Treatments to modify a piezoelectric or electrostrictive property, e.g. polarisation characteristics, vibration characteristics or mode tuning by polarising
• H10N 30/00 - Piezoelectric or electrostrictive devices

Abstract

The present invention relates to an elastic wave device, in particular a shear wave device, comprising a piezoelectric material (3), in particular a ferroelectric material with first domains (3a) having a first polarisation direction (13a) and second domains (3b) having a second polarisation direction (13b), the first direction (13a) being opposite to the second direction, wherein the first and second domains (3a, 3b) alternate periodically in a direction d, referred to as the periodic direction, which is perpendicular to the normal n to the surface of the piezoelectric material (3), and a pair of interdigitated comb electrodes (15a, 15b) above, in particular on, the piezoelectric material (3), the respective comb teeth (17a1 to 17a3 and 17b1 to 17b3) of which extend essentially perpendicular to the periodic direction d and to the normal n to the surface of the substrate.

IPC Classes  ?

• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elementsElectromechanical resonators Details
• H03H 3/10 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves for obtaining desired frequency or temperature coefficient
• H03H 9/64 - Filters using surface acoustic waves
• H10N 30/045 - Treatments to modify a piezoelectric or electrostrictive property, e.g. polarisation characteristics, vibration characteristics or mode tuning by polarising
• H10N 30/00 - Piezoelectric or electrostrictive devices

Abstract

The present invention relates to a method of manufacturing a donor substrate for the manufacture of a Piezoelectric on Insulator, POI, structure, comprising providing a support substrate, forming a block of piezoelectric material on or over the support substrate, wherein the piezoelectric material comprises or consists of one of lithium tantalate and lithium niobate, chemical-mechanical polishing, CMP, the block of piezoelectric material to obtain a piezoelectric substrate and implanting a species into the piezoelectric substrate to obtain a weakened layer in the piezoelectric substrate. The CMP is performed by means of a CMP pad comprising a sub pad with a hardness of more than 45 shore A.

IPC Classes  ?

• H10N 30/073 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
• H10N 30/086 - Shaping or machining of piezoelectric or electrostrictive bodies by machining by polishing or grinding

Abstract

The present invention relates to a method of refreshing a donor substrate for the manufacture of a Piezoelectric on Insulator, POI, structure, comprising providing the donor substrate to be refreshed comprising a support substrate and a first piezoelectric substrate formed over the support substrate comprising or consisting of one of lithium tantalate and lithium niobate, wherein the first piezoelectric substrate is a second piezoelectric substrate from which a piezoelectric layer has been transferred to a target substrate and chemical-mechanical polishing, CMP, the first piezoelectric substrate to obtain a refreshed donor substrate comprising a refreshed piezoelectric substrate, wherein the CMP comprises removing a layer of the first piezoelectric substrate with a thickness of at most 2 µm, in particular, at most 1.2 µm.

IPC Classes  ?

• H10N 30/073 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
• H10N 30/086 - Shaping or machining of piezoelectric or electrostrictive bodies by machining by polishing or grinding

Abstract

The present invention relates to a method of manufacturing a Piezoelectric on Insulator, POI, structure, comprising providing a donor substrate comprising a piezoelectric substrate, wherein the piezoelectric substrate comprises or consists of one of lithium tantalate and lithium niobate, transferring a piezoelectric layer from the piezoelectric substrate to a target substrate, and polishing the piezoelectric layer transferred to the target substrate with a chemical mechanical polishing, CMP, slurry, wherein the CMP slurry consists of an aqueous suspension of amorphous silicon with a weight percent of the amorphous silicon in the range of 4 to 18.

IPC Classes  ?

• H10N 30/073 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
• H10N 30/086 - Shaping or machining of piezoelectric or electrostrictive bodies by machining by polishing or grinding

Abstract

The invention relates to a method for manufacturing a substrate (100), referred to as a donor pseudo-substrate, comprising a plurality of tiles (1) arranged at a distance from one another on a support substrate (3), comprising the steps of: - arranging, on the support substrate (3), said tiles (1) and an intermediate substrate (2) comprising a plurality of through-openings (20), such that each tile (1) extends into a respective through-opening (20) of the intermediate substrate, and - performing chemical-mechanical polishing of the tiles (1) arranged in the openings of the intermediate substrate.

IPC Classes  ?

• H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns

Abstract

The invention relates to a method for transferring chips onto a receiver substrate from tiles arranged on a support substrate, comprising: - forming a substrate (10), referred to as the pseudo-donor substrate, comprising the support substrate (2) and the tiles (1), wherein two adjacent tiles are spaced apart by a first distance (d1), - carrying out chemical mechanical polishing on the tiles, - forming a weakened zone in at least one portion of the tiles so as to delimit a respective chip, - bonding the pseudo-donor substrate to the receiver substrate via the tiles, - detaching the tiles along the weakened zone so as to transfer a respective chip onto the receiver substrate, two adjacent chips being spaced apart by a second distance greater than the first distance (d1), - before the bonding step, locally roughening the surface of the tiles and/or the receiver substrate to make regions of the surface unsuitable for bonding, so as to prevent the chips from being transferred in said regions.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials

Abstract

The invention relates to a structure (Strc) capable of forming a quantum device, comprising: a silicon carrier substrate (Car); a first layer (Si-L1) of silicon isotope 28Si; a layer (Ox) of silicon oxide; a second layer (Si-L2) of silicon isotope 28Si, wherein the structure is formed by the carrier substrate (Car), the first layer (Si-L1) of silicon isotope 28Si, the layer (Ox) of silicon oxide, and the second layer (Si-L1) of silicon isotope 28Si, stacked in this order, wherein the first layer (SiL1) and the second layer (Si-L2) of silicon isotope 28Si are each made up of at least 99.92% of silicon isotope 28Si.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/762 - Dielectric regions

Abstract

The invention relates to a method for producing a substrate (100), referred to as a donor pseudo-substrate, comprising a plurality of first blocks (1) arranged at a distance from one another on a carrier substrate (3), wherein the method comprises: - arranging, on the carrier substrate (3), the first blocks (1) and a plurality of second blocks (2) arranged between the first blocks (1) such that each edge of each first block (1) faces at least one second block (2), wherein the first blocks (1) comprise a first material and the second blocks (2) comprise a second material different from the first material; and - chemical-mechanical polishing of the first and second blocks (1, 2).

IPC Classes  ?

• H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns

Abstract

The invention relates to a method for producing a SOI structure, comprising the following steps: a) providing an initial substrate made of monocrystalline silicon, having an interstitial oxygen content of between 15 and 27 ppma according to standard ASTM'79 and a resistivity of less than 200 ohms.cm, the initial substrate being intended to form a carrier substrate for the SOI structure after having undergone the subsequent step b); b) applying a sequence of heat treatments to the initial substrate while it is devoid, at least on a front face, of a silicon oxide layer other than optionally a native oxide layer, the sequence consisting of: - a first heat treatment defined by a plateau at a temperature higher than 1200°C and lower than 1280°C and with a duration of between 1 second and 60 seconds, by a temperature decrease ramp of between 10°C/s and 70°C/s, and by an argon or argon-hydrogen atmosphere; followed by - a second heat treatment defined by a plateau at a temperature of between 900°C and 1100°C, without an intermediate step before this temperature, under a neutral or oxidising atmosphere, in order to form a carrier substrate comprising: - a stripped surface layer, with a thickness greater than 40 μm and having a micro-defect concentration (BMD) of less than 108/cm3, and - an enriched deep layer, under the stripped surface layer, having a micro-defect concentration (BMD) of between 2.108/cm3and 5.1010/cm3. The invention also relates to a carrier substrate and a SOI structure including the carrier substrate.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/322 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to modify their internal properties, e.g. to produce internal imperfections
• H01L 21/762 - Dielectric regions

Abstract

Disclosed is a carrier (100) intended to be split by laser radiation, comprising a carrier substrate (Sprt); on the carrier layer, a splitting layer (Sep) formed from an inorganic material of thickness between 10 nm and 100 nm; and a layer (Brg) forming a Bragg mirror, the splitting layer (Sep) being interposed between the carrier substrate (Sprt) and the layer (Brg) forming the Bragg mirror, the carrier being configured in such a way that the carrier substrate is substantially transparent to laser radiation of a certain wavelength, the layer forming the Bragg mirror is substantially reflective with respect to the laser radiation, and the splitting layer (Sep) can absorb some of the laser radiation, such that the carrier can be split into two parts level with the splitting layer (Sep) under the action of the laser radiation.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

Abstract

CarCarDonDon) respective overcoat layers (Cap1, Cap2) on the two superlattices (Stck1, Stck2); and assembling (660) the two superlattices (Stck1, Stck2) by placing their respective overcoat layers (Cap1, Cap2) in contact, so that together they form a bonding layer, the first overcoat layer (Cap1) and the second overcoat layer (Cap2) each having a thickness of less than 2 nm.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H10D 88/00 - Three-dimensional [3D] integrated devices
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H01L 21/762 - Dielectric regions

Abstract

The invention relates to a method for controlling the quality of a composite structure comprising a thin layer made of single-crystal silicon carbide placed on a carrier substrate made of polycrystalline silicon carbide, the method comprising: a) inspection of a free surface (10a) of the thin layer (10) using a technique coupling visible-light confocal microscopy and photoluminescence imaging, making it possible to detect defects, called secondary defects, b) preliminary identification of the secondary defects, by similarity, on the basis of their visible-light image, by virtue of an image recognition algorithm trained on various types of defects such as holes, bubbles, scratches, and defects of crystalline origin; at the end of step b), each secondary defect is associated with one identified type of defect, with a certain level of similarity, c) final classification of at least certain secondary defects by application of the following first conditions: - if the level of similarity associated with a secondary defect is greater than a high level, said secondary defect is definitively classified in the identified type of defect, - if the level of similarity associated with the secondary defect is between a low level and the high level, the photoluminescence image of said defect is analysed; if the secondary defect is associated with a labelled type of PL defect, said secondary defect is definitively classified in the identified type of defect, - in all other cases, the secondary defect is definitively classified as not a defect.

IPC Classes  ?

• H01L 21/66 - Testing or measuring during manufacture or treatment
• C30B 29/36 - Carbides
• G01N 21/64 - FluorescencePhosphorescence
• G01N 21/95 - Investigating the presence of flaws, defects or contamination characterised by the material or shape of the object to be examined
• C30B 25/20 - Epitaxial-layer growth characterised by the substrate the substrate being of the same materials as the epitaxial layer

Abstract

The invention relates to a process for fabricating a composite structure comprising a thin layer made of single-crystal silicon carbide placed on a carrier substrate made of polycrystalline silicon carbide, the process comprising the following steps: 1) providing at least one donor substrate made of single-crystal silicon carbide, having a front side and a rear side, the front side potentially having defects, called primary defects; 2) controlling the quality of the - at least one - donor substrate by means of a photoluminescence-based imaging technique, so as to extract a map of the front side, called the first map, cataloguing the primary defects identified as being of micro-hole type, of the complex type consisting of star stacking faults or of point-defect type; 3) transferring a thin layer, obtained from a surface layer of the - at least one - donor substrate, onto a carrier substrate made of polycrystalline silicon carbide, in order to obtain a composite structure and a residual donor substrate; 4) inspecting a free surface of the thin layer of the composite structure by means of a technique for inspecting for defects by means of scattering of an ultraviolet laser beam, so as to extract a map of the free surface, called the second map, cataloguing defects called secondary defects; 5) grading the composite structure, this including a comparison of the first map and of the second map.

IPC Classes  ?

• H01L 21/66 - Testing or measuring during manufacture or treatment
• G01N 21/64 - FluorescencePhosphorescence
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• G01N 21/84 - Systems specially adapted for particular applications

Abstract

CarDonDon) a second superlattice (Stck2) on a second substrate by stacking a plurality of second channel layers alternating with a plurality of second sacrificial layers; and assembling (560) the second superlattice (Stck2) on the first superlattice (Stck1) at a dielectric separation layer which separates the first superlattice (Stck1) and the second superlattice (Stck2) and keeps them attached to one another, the first superlattice (Stck1), the separation layer and the second superlattice (Stck2) being stacked in this order.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H10D 88/00 - Three-dimensional [3D] integrated devices
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 62/822 - Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H01L 21/762 - Dielectric regions

Abstract

CarDonDonDon) a weakening plane (Imp) in the second substrate; assembling (560) the seed layer (Init) on the first superlattice (Stck1) at a dielectric separation layer that separates the first superlattice (Stck1) and the seed layer (Init) and keeps them attached to each other; removing (570A) a portion of the second substrate by fracturing the second substrate at the weakening plane (Imp) after the assembly step (560); exposing (570B) the seed layer (Init) after the step (570A) of fracturing the second substrate; and forming (580) the second superlattice (Stck2) on the exposed seed layer (Init).

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H10D 88/00 - Three-dimensional [3D] integrated devices
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H01L 21/762 - Dielectric regions

Abstract

The invention relates to a carrier (1) for a composite substrate (S). The carrier comprises a base substrate and a trapping layer (3a) made of polycrystalline silicon arranged on the base substrate (2). The trapping layer has electric traps of a first type having an activation energy of 0.383 eV within a tolerance of 0.008 eV, and an effective capture cross-section for holes and electrons of less than 10^-16 cm^2. The trapping layer has electrical traps of a second type having an activation energy of 0.428 eV within a tolerance of 0.016 eV, and an effective capture cross-section for holes and electrons of less than 10^-16 cm^2.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/762 - Dielectric regions
• H01L 21/66 - Testing or measuring during manufacture or treatment

Abstract

moynuumoynuuu) are determined, prior to carrying out steps b), c) and d), on the basis of a model that relates them to an etched mean thickness of the surface layer and to a mean etching non-uniformity defined by the difference between an etched mean thickness in a central region and in a peripheral region of the surface layer.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
• H01L 21/762 - Dielectric regions

Abstract

The invention relates to a method for manufacturing an active layer of monocrystalline silicon carbide by homoepitaxy on a composite structure, the method comprising the following steps: 1) providing a composite structure comprising a growth layer made of monocrystalline silicon carbide extending in a main plane and arranged on a support substrate, the growth layer being delimited by a peripheral perimeter and having a first thickness along an axis normal to the main plane; 2) forming a local barrier in or on the growth layer, the local barrier extending at a distance from and along the peripheral perimeter, and corresponding to a physical discontinuity of the growth layer chosen from: - a proeminent relief induced by the presence of a material on the growth layer, said material being different from that of the growth layer, - a recessed relief corresponding to an etched region of the growth layer, or - an amorphous domain or domain of crystallinity different from the rest of the growth layer, the local barrier having a thickness, along the axis normal to the main plane, less than the first thickness; 3) epitaxial growth of the active layer on the growth layer.

IPC Classes  ?

• H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth

Abstract

The invention relates to a substrate and the production method therefor for producing a bidirectional switch, the method comprising: - transferring, to the front face of a carrier substrate, a first seed layer (21) made of a wide-bandgap polar semiconductor material; - transferring, to the rear face of the carrier substrate, a second seed layer (22) made of the wide-bandgap polar semiconductor material, wherein these transfers are carried out so as to expose a surface of a first type (F1) of the first seed layer (21) and a surface of the first type (F1) of the second seed layer (22), and wherein a surface of a second type (F2) of the first seed layer (21) and a surface of the second type (F2) of the second seed layer (22) are at the interface with the front face and the rear face of the support substrate, respectively.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• H10D 12/01 - Manufacture or treatment
• H10D 30/01 - Manufacture or treatment
• H10D 30/66 - Vertical DMOS [VDMOS] FETs
• H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
• H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
• H10D 88/00 - Three-dimensional [3D] integrated devices

Abstract

The present invention relates to a method for producing a composite structure, the method comprising: (a) forming a temporary substrate (3') comprising a carrier substrate (3), wherein a plurality of tile portions (P'1-P'3) or a layer of interest (20) made of a first material are arranged on the carrier substrate (3); (b) forming a removable interface (5) arranged between the carrier substrate (3) and the tile portions or the layer of interest, or in or on the tile portions or the layer of interest; (c) assembling the temporary substrate (3') with a receiver substrate (4) made of a second material that is different from the first material, via the tile portions or the layer of interest; and (d) removing the carrier substrate (3) by dismantling the removable interface (5) so as to transfer at least one portion of the tile portions (P'1-P'3) or of the layer of interest (20) to the receiver substrate (4) to form the composite structure.

IPC Classes  ?

• H01L 21/6835 -
• H01L 21/76254 -
• H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
• H01L 21/762 - Dielectric regions

Abstract

22111211 = 2.85×1018cm-322 = 5.40×1020cm-3, - an interface zone, between the carrier substrate and the working layer, comprising nodules and regions of direct contact between the working layer and the carrier substrate, the nodules comprising a metal or semiconductor material other than silicon carbide, the interface zone having an average resistivity of less than or equal to 0.01 mohm.cm2, a dopant concentration profile along a thickness of the semiconductor structure: - being in the form of a step, and - being devoid of a doping peak in the interface zone, or - exhibiting a doping peak in the interface zone, the extremum of which corresponds to a third dopant concentration equal to the second dopant concentration to within plus or minus 10%. The invention also relates to a process for fabricating such a semiconductor structure.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials

Abstract

The present invention relates to an elastic wave device comprising a piezoelectric material (3) with first domains (3a1, 3a2) of a first polarization direction (13a) and second domains (3b1, 3b2) with a second polarization direction (13b), the first direction being opposite to the second direction, in which the first and second domains are periodically alternated along a direction, called periodic direction, perpendicular to the surface normal of the piezoelectric material, and a pair of interdigitated comb electrodes (15a, 15b), the respective comb teeth (17a1, 17a2, 17b1, 17b2) of which extend mainly in the periodic direction, and to a method for manufacturing such an elastic wave device.

IPC Classes  ?

• H03H 3/08 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elementsElectromechanical resonators Details
• H03H 9/145 - Driving means, e.g. electrodes, coils for networks using surface acoustic waves

Abstract

TTFF) of formation of the carbon layer.

IPC Classes  ?

• C30B 29/36 - Carbides
• C30B 33/02 - Heat treatment
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

The invention relates to a process for transferring a thin layer to a carrier substrate, comprising: - joining a donor substrate (1) and the carrier substrate (2) by direct bonding of their respective front sides (1a, 2a) via a bonding interface (3), to form a bonded assembly (100) having an unbonded local region (31) within this bonding interface (3), the donor substrate (1) further comprising a buried fragile plane (11), - splitting along the buried fragile plane (11), the splitting being initiated in the unbonded local region (31) after growth of microcracks in said plane (11) by thermal activation, and leading to the transfer of a thin layer (10) from the donor substrate (1) to the carrier substrate (2). The process is noteworthy in that the unbonded local region (31) is generated by at least one rough region (31a) produced by scanning a laser beam over at least one of the front sides (1a, 2a) of the donor substrate (1) and carrier substrate (2) before they are joined, the scan covering an area of at least 100 microns by 100 microns and of at most 500 microns by 500 microns.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• H01L 21/268 - Bombardment with wave or particle radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
• H01L 21/762 - Dielectric regions

Abstract

The invention relates to a method for manufacturing a diamond substrate, or a III-V material substrate, for microelectronic applications, the method comprising: - bonding a plurality of monocrystalline diamond tiles or III-V material tiles (20) onto a carrier substrate (1), each tile being spaced apart from the adjacent tiles so as to expose a lateral surface (S2) of each tile; - epitaxially growing diamond or the III-V material from the lateral surface and the upper surface of each tile until a continuous layer (2) of monocrystalline diamond or III-V material is formed and extends over the plurality of tiles (20); - forming, by implanting atomic species, a weakened zone (21) in the continuous layer (2) of monocrystalline diamond or III-V material to define a surface layer (22) to be transferred; - bonding the continuous layer (2) of monocrystalline diamond or III-V material onto a receiver substrate (3); - detaching the continuous layer (2) of monocrystalline diamond or III-V material along the weakened zone (21) so as to transfer the surface layer (22) of monocrystalline diamond or III-V material onto the receiver substrate (3) to form the diamond or III-V material substrate.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

The present disclosure relates to an intermediate substrate (10) for the manufacture of a semiconductor substrate, the intermediate substrate successively comprising: a a first semiconductor layer (2); b a first thermal barrier layer (5); c a support (13) comprising an absorption layer (3) configured to absorb laser radiation in a given wavelength range, the temperature of the absorption layer (3) increasing as it absorbs the laser radiation, and a separation zone (8) adjacent to the absorption layer (3) configured to thermally degrade due to the increase in temperature of the absorption layer, so as to separate at least part of the support (13) from the rest of the intermediate substrate (10).

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• C30B 33/06 - Joining of crystals
• H01L 21/762 - Dielectric regions
• H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping

Abstract

The invention relates to a semiconductor structure (SC) comprising a support (1a) and a dielectric layer (1b) directly disposed on the support (1a). At least one pFET structure is directly residing on the dielectric layer (1b), each pFET structure comprising a first stack of channel nanosheets made of compressively strained silicon germanium and a pFET gate structure encapsulating each channel nanosheet of the first stack. At least one nFET structure is directly residing on the dielectric layer, each nFET structure comprising a second stack of channel nanosheets made of silicon and a nFET gate structure encapsulating each channel nanosheet of the second stack.

IPC Classes  ?

• H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
• H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/786 - Thin-film transistors

Abstract

The invention relates to a polycrystalline silicon carbide carrier for a substrate intended to accommodate a power semiconductor device. The carrier has a first face, referred to as the "front face", and a second face, referred to as the "rear face", and comprises a first surface layer arranged directly under the front face and having a resistivity higher than or equal to 1 ohm.cm and a second surface layer arranged directly under the rear face and having a resistivity strictly lower than 1 ohm.cm.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/762 - Dielectric regions

Abstract

The invention relates to a method for producing a donor substrate (1) for transferring a piezoelectric layer onto a support substrate, which comprises the following successive steps: • (a) providing a piezoelectric substrate (5) and a manipulation substrate (2); • (b) depositing a photo-polymerisable adhesive layer (6) on a main face of the manipulation substrate (2) or the piezoelectric substrate (5); • (c) bonding the piezoelectric substrate (5) with the manipulation substrate (2) via the adhesive layer (6) to form a heterostructure (7); • (d) irradiating the heterostructure (7) with a luminous flux to polymerise the adhesive layer (6); • (e) thermally treating the irradiated heterostructure (7); and • (f) thinning the piezoelectric substrate (5) by its face opposite the manipulation substrate (2), so as to form the donor substrate (1).

IPC Classes  ?

• H10N 30/072 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
• H10N 30/073 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
• H03H 3/007 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks

Abstract

The invention relates to a final substrate (S) comprising, consecutively and in contact with one another, an upper layer (5) made of semiconductor material, a dielectric layer (4) having a thickness greater than 200 nm, an electrical charge trapping layer (2) and a base substrate (3). The final substrate (S) has a curvature of less than 60 micrometres, preferably less than 40 micrometres. An exposed surface of the upper layer (5) has a roughness of less than 0.3 nm as a root mean square measurement over a field of 30 micrometres by 30 micrometres. The invention also relates to a method for preparing such a substrate.

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

The invention relates to a process comprising:  providing a heterostructure comprising a growth substrate (1), an interlayer (2) of two-dimensional material and an epitaxial semiconductor layer (3);  providing a rigid substrate (4) comprising a weakened plane (5);  producing a first assembly by bonding the rigid substrate to the heterostructure, the first side (F) and the epitaxial layer (3) being at the bonding interface;  splitting the first assembly at the interlayer (2) of two-dimensional material, so as to obtain a second assembly resulting from transfer of the epitaxial layer (3) from the heterostructure to the rigid substrate (4);  producing a third assembly by bonding the second assembly to a target substrate (7), the epitaxial layer (3) being at the bonding interface;  splitting the third assembly along the weakened plane (5) of the rigid substrate (4).

IPC Classes  ?

• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

The invention relates to a method for manufacturing a plurality of polycrystalline silicon carbide substrates (200), the method comprising the following steps: • forming a multilayer structure by alternately depositing a plurality of polycrystalline silicon carbide layers (20, 21, 22, 23, 24) and a plurality of separation layers (30, 31, 32, 33) on at least one face of a temporary support substrate (10); • detaching each polycrystalline silicon carbide layer (20, 21, 22, 23, 24) from the multilayer structure by removing the temporary substrate (10) and each separation layer (30, 31, 32, 33) to form a respective polycrystalline silicon carbide substrate (200).

IPC Classes  ?

• C30B 25/18 - Epitaxial-layer growth characterised by the substrate
• C30B 29/36 - Carbides
• C30B 33/02 - Heat treatment
• C30B 33/06 - Joining of crystals

Abstract

The invention relates to a method for preparing a thin single-domain layer (3') made of ferroelectric material, the method comprising, between a step of splitting a donor substrate (1) at a weakened plane (2) in order to form a first layer (3) and a sequence for finishing the first layer (3), the application of a treatment to the free face (8) of the first layer (3) in order to produce a hydrogen concentration of greater than 2.0E21 at/cm^3 in a surface thickness of the first layer (3).

IPC Classes  ?

• H10N 30/073 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials

Abstract

The invention relates to a method for producing a substrate (300) comprising a polycrystalline silicon carbide layer (30, 30A, 30B) and a monocrystalline silicon carbide layer (20, 20A, 30B) in direct contact with the polycrystalline silicon carbide layer, said method successively comprising the following steps of: - transferring a first monocrystalline silicon carbide layer (20, 20A) onto a front face of a temporary graphite carrier substrate (10), - depositing polycrystalline silicon carbide on the first monocrystalline silicon carbide layer (20, 20A) to form the polycrystalline silicon carbide layer (30, 30A), - removing the temporary graphite carrier substrate (10).

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

The invention relates to a method for transferring a layer onto a carrier substrate, the method comprising: a) a step of forming cavities in a carrier substrate, the cavities opening out via a main face; b) a step of transferring a sealing layer that is intended to seal all of the cavities formed during step a); step a) being carried out such that all of the cavities are distributed regularly over a main region of the main face and such that the main face comprises a peripheral ring free of cavities and inside which the main region is circumscribed, the peripheral ring extending from the edge of the carrier substrate over a length L that is shorter than a predetermined length Lp below which the sealing layer is free of regions that have not been transferred in the peripheral ring.

IPC Classes  ?

• B81C 1/00 - Manufacture or treatment of devices or systems in or on a substrate

Abstract

The present invention relates to a method for manufacturing a structure comprising a plurality of cavities confined between a thin layer and a carrier substrate, the method comprising the following steps: a) providing a donor substrate and a carrier substrate; b) implanting first light species into the donor substrate to form a uniform buried weakened plane which defines, together with the front face of the donor substrate, the thin layer to be transferred; c) locally implanting second species into the donor substrate so as to introduce these species into the uniform buried weakened plane only at second regions so as to form a functional buried weakened plane having: first regions comprising the first light species and not the second species, and the second regions comprising the first light species and the second species; d) forming a plurality of cavities that open onto a front face of the donor substrate or of the carrier substrate; e) joining, by direct bonding, the donor substrate to the carrier substrate, via their respective front faces, to form a bonded structure in which the cavities are vertically in line with either the first regions or the second regions of the functional buried weakened plane; f) applying a heat treatment to the bonded structure in order to cause spontaneous separation along the functional buried weakened plane and form the structure on the one hand and the rest of the donor substrate on the other hand.

IPC Classes  ?

• B81C 1/00 - Manufacture or treatment of devices or systems in or on a substrate

Abstract

1111122222111222122 integers.

IPC Classes  ?

• H01S 5/02 - Structural details or components not essential to laser action
• H01S 5/183 - Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]

Abstract

422220200400400 is greater than 50%, preferably greater than 80%. The invention also relates to a method for producing such a composite structure. Figure to be published with the abstract: No figure

IPC Classes  ?

• C23C 16/01 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes on temporary substrates, e.g. on substrates subsequently removed by etching
• C23C 16/32 - Carbides
• C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
• C23C 16/56 - After-treatment
• C30B 28/14 - Production of homogeneous polycrystalline material with defined structure directly from the gas state by chemical reaction of reactive gases
• C30B 29/36 - Carbides
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• C30B 33/06 - Joining of crystals
• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
• H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form

Abstract

A carrier (Sprt) for a composite substrate, the carrier (Sprt) comprising a layer (Trap) for trapping electrical charges, in contact with a base carrier (BSprt), the trapping layer (Trap) comprising a low permittivity layer made of a material having a relative dielectric permittivity lower than silicon dioxide, and the material which has a relative dielectric permittivity lower than silicon dioxide being SiOC or SiOCH.

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

The present disclosure relates to a method for forming a weakened zone (5) in a semiconductor substrate (6), successively comprising the following steps: a. forming a screen layer (4) having a non-planar controlled profile on a first face (61) of the substrate, b. implanting species through the screen layer and the first face (61) of the substrate to form the weakened zone, the profile of the screen layer being selected to compensate for a non-uniformity in the implantation depth of the species so that the weakened zone (5) is substantially located in a plane parallel to the first face (61).

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/762 - Dielectric regions

Abstract

The present disclosure relates to a method for reducing the boron concentration in a semiconductor layer (12) of a semiconductor-on-insulator substrate (1), the method involving: - at least one heat treatment cycle, each cycle comprising thermal oxidation of the semiconductor layer (12) so as to form an oxide layer (120) on the semiconductor layer (12), wherein, by segregation of the boron, boron atoms from the semiconductor layer (12) diffuse into the oxide layer (120) so as to create a boron concentration deficit in the semiconductor layer (12) at the interface with the oxide layer (120), and - removing the oxide layer (120), wherein the thermal oxidation comprises a temperature increase, under an inert atmosphere, to a temperature above a thermal oxidation target temperature, followed by a temperature decrease to said thermal oxidation target temperature so as to form a temperature gradient in the substrate at which an oxide layer (120) formation rate is higher in the center of the semiconductor layer than at the edge.

IPC Classes  ?

• H01L 21/225 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regionsRedistribution of impurity materials, e.g. without introduction or removal of further dopant using diffusion into, or out of, a solid from or into a solid phase, e.g. a doped oxide layer
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/322 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to modify their internal properties, e.g. to produce internal imperfections
• H01L 21/762 - Dielectric regions

Abstract

lay laylay) and the first volume (V1) is disposed between this face of the ferroelectric layer and the second volume (V2); and wherein the second volume (V2) has a hydrogen concentration, known as the polarity reversal concentration, greater than the first volume (V1), and the polarity reversal concentration is between 10 19and 10 22 hydrogen atoms per cubic centimeter.

IPC Classes  ?

• H10N 30/045 - Treatments to modify a piezoelectric or electrostrictive property, e.g. polarisation characteristics, vibration characteristics or mode tuning by polarising
• H10N 30/072 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
• H10N 30/073 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
• H03H 9/02 - Networks comprising electromechanical or electro-acoustic elementsElectromechanical resonators Details

Abstract

Structure (Struct) comprising a ferroelectric layer (Ferrolay) having a first polarization (P1) in a first area and a second polarization (P2), opposite to the first polarization, in a second area (V) different from the first area, the first polarization and the second polarization being oriented perpendicularly or obliquely to the ferroelectric layer, the second polarization area having a hydrogen concentration greater than the first polarization area, the structure further comprising a support (Sprt) and a dielectric layer (Diel) disposed between this support and the ferroelectric layer.

IPC Classes  ?

• H10N 30/045 - Treatments to modify a piezoelectric or electrostrictive property, e.g. polarisation characteristics, vibration characteristics or mode tuning by polarising
• H10N 30/853 - Ceramic compositions

Abstract

The invention relates to a method for producing a semiconductor substrate having an epitaxially deposited layer, comprising the following successive steps: - etching (ETCH) a susceptor of an epitaxy reactor; - coating (COAT) the susceptor; - placing a semiconductor substrate on the susceptor; - depositing (EPI) an epitaxial layer on the semiconductor substrate. The method also comprises, after coating and before deposition, exposing (ISO) the susceptor to an oxygen-containing gas mixture. The method further comprises, after placement and before deposition, a baking step (BAKE) involving baking the semiconductor substrate, which, except on the underside of the semiconductor substrate, removes an oxide layer formed by exposing the susceptor to an oxygen-containing gas mixture.

IPC Classes  ?

• C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
• C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
• C30B 25/12 - Substrate holders or susceptors

Abstract

Device comprising a ferroelectric surface layer (20) containing lithium; a dielectric layer (16) comprising an oxide and arranged in contact with the ferroelectric surface layer; and a substrate (10) in contact with the dielectric layer, the substrate comprising a charge trapping layer (14) arranged on a support (12), the charge trapping layer (14) being arranged between the support (12) and the dielectric layer (16), the dielectric layer (16) having a thickness of between 150 nm and 500 nm, preferably between 150 nm and 300 nm; and a nitrogen concentration in the dielectric layer (16) and a surface roughness of the charge trapping layer (14) being such that the charge trapping layer (14) has a lithium content of less than 5x1011at/cm2.

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
• H10N 30/072 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
• H01L 21/3105 - After-treatment
• H01L 21/321 - After-treatment

Abstract

The invention relates to a process for manufacturing a multilayer structure, comprising the following steps: - providing a carrier substrate (40) comprising a carrier layer (41) and a porous silicon layer (42); - providing a donor substrate (50) comprising a buried fragile plane (50B) and a surface layer (51); - assembling (S3) the carrier substrate (40) and the donor substrate (50) by bonding, the surface layer (51) of the donor substrate being placed in contact with the carrier substrate; - separating the surface layer (51) from the donor substrate (50) via fracture along the buried fragile plane (50B); at least one of the carrier and donor substrates (40, 50), called the degraded substrate, comprises a degraded portion (60) so as to prevent it from bonding to the other of the carrier and donor substrates (50, 40) in the assembly step, the degraded portion (60) having an annular or substantially annular shape and being located less than 25 mm from the edge of said degraded substrate.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• H01L 21/762 - Dielectric regions

Abstract

The present disclosure relates to a method for manufacturing an image sensor for detecting visible light and short-wave infrared rays, characterised in that the method comprises the following steps of: a. providing a support substrate (1, 1') comprising a first semiconductor material; b. forming, in the support substrate (1, 1'), cavities (5) in order to define pixels (11, 11') sensitive to visible light in the first semiconductor material between the cavities (5); c. forming an electrically insulating protective layer (4) at least on the lateral surfaces of each pixel (11, 11') sensitive to visible light; growing, in the cavities (5), a second material that is different from the first material, so as to form pixels (12, 12') sensitive to short-wave infrared rays.

IPC Classes  ?

• H01L 27/146 - Imager structures

Abstract

The invention relates to a method for manufacturing two substrates called donor pseudo-substrates (1, 2) each comprising at least two tiles on a carrier substrate, the method comprising the following successive steps: - placing, on a first carrier substrate (3), at least two tiles (P1, P2), each tile having an initial thickness greater than or equal to 300 μm, so as to form a first donor pseudo-substrate (1) comprising the at least two tiles, - bonding said first donor pseudo-substrate (1) onto a second carrier substrate (4) via the tiles (P1, P2), - splitting the tiles into two portions (P'1, P'2, P''1, P''2) of a first thickness (e1) and a second thickness (e2) so as to keep a first portion (P'1, P'2) of said tiles having the first thickness (e1) on the first donor pseudo-substrate and to transfer a second portion (P''1, P''2) of the tiles having the second thickness (e2) onto the second carrier substrate (4) so as to form a second donor pseudo-substrate (2), the second thickness (e2) being between 20% and 80% of the initial thickness of the tiles of the first donor pseudo-substrate.

IPC Classes  ?

• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H10N 30/072 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies

Abstract

The present invention relates to a method for producing a composite structure, the method comprising: (a) forming a temporary substrate (20) comprising an intermediate substrate (2) and a plurality of tiles (P1, P2, P3) of a first material; (b) joining the temporary substrate to a receiver substrate (3) made of a second material, different from the first material, via the tiles; and (c) removing the intermediate substrate (2) in order to transfer at least a portion (P'1, P'2, P'3) of the tiles to the receiver substrate. The receiver substrate comprises a main surface from which cavities (01, 02, 03) extend, the receiver substrate being joined to the temporary substrate on the main surface side such that each tile is received in a respective cavity. Once the intermediate substrate has been removed, the free surface of the tile portions is substantially aligned with the main surface of the receiver substrate.

IPC Classes  ?

• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• H01L 21/762 - Dielectric regions
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping

Abstract

The invention relates to a method for preparing a single-domain thin film (4) of ferroelectric material comprising lithium, the method comprising the provision of a first layer (8) that has a free surface (9). According to the invention, the preparation method comprises a surface treatment that exposes the free face (9) of the first layer (8) to a treatment atmosphere comprising at least 0.02% carbon dioxide in order to form a lithium-rich passivation layer and a treatment for removing the lithium-rich passivation layer.

IPC Classes  ?

• H10N 30/072 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
• H10N 30/073 - Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
• H01L 21/762 - Dielectric regions

Abstract

The invention relates to a method for stabilizing a surface of a semiconductor material, in particular a monocrystalline semiconductor material, against the formation of terraces and/or beads, said method comprising the formation, on said surface, of a vitreous carbon layer (30) in the gaseous phase at a pressure greater than or equal to 80 kPa (800 mbar).

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

22) ratio and temperature conditions suitable for forming carbon inclusions (1) in the layer of silicon carbide, and · assembling the support substrate (10) and a surface layer (20) made of a monocrystalline material.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials

Abstract

laylay) of boron arsenide BAs having two dimensions each of at least 2 cm in, respectively, two directions normal to each other and within the extension plane.

IPC Classes  ?

• C30B 25/18 - Epitaxial-layer growth characterised by the substrate
• C30B 29/40 - AIIIBV compounds
• C30B 33/06 - Joining of crystals
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body

Abstract

The invention relates to a carrier (1) for a composite substrate, the carrier (1) comprising an interlayer (3) arranged on a base substrate (2). The interlayer (3) comprises a trapping layer (3a) in contact with the base substrate (2), the trapping layer being formed of a silicon-rich oxide consisting of silicon at an atomic concentration of between 30% and 77%, of oxygen at an atomic concentration of between 8% and 40% and of nitrogen at an atomic concentration of between 8% and 45%. The invention also relates to a composite substrate (S) incorporating such a carrier (1) and to a method for producing this composite substrate (S).

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

The invention relates to a carrier (1) for a composite substrate, the carrier (1) comprising an interlayer (3) arranged on a base substrate (2). The interlayer (3) comprises a trapping layer (3a) in contact with the base substrate (2), which trapping layer is made of a silicon-rich oxide that has an atomic concentration of silicon of between 40% and 99.9%. The interlayer also comprises a dielectric layer (3b) in contact with the trapping layer (3a). A transition zone arranged between the trapping layer (3a) and the dielectric layer (3b) has a thickness greater than 50 nm in which the atomic concentration of silicon continuously varies. The invention also relates to a composite substrate (S) incorporating such a carrier (1) and to a method for producing the carrier (1).

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

The invention relates to a carrier (1) for a composite substrate, the carrier (1) comprising an interlayer (3) arranged on a base substrate (2). The interlayer (3) comprises a trapping layer (3a) in contact with the base substrate (2), which trapping layer is formed of a silicon-rich oxide consisting of silicon at an atomic concentration of silicon of between 70% and 90% and oxygen at an atomic concentration of between 10% and 30%. The invention also relates to a composite substrate (S) incorporating such a carrier (1) and to a method for producing this composite substrate (S).

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

One aspect of the invention relates to a method for producing a semiconductor stack (10), comprising, from a first silicon layer (11), referred to as a support layer, the following steps: - forming a silicon carbide layer (12), extending over the support layer (11); and - annealing the layers until cavities (13) are formed, each cavity (13) extending into the support layer (11), from the silicon carbide layer (12).

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
• H01L 21/762 - Dielectric regions

Abstract

xyy)-based diffusion barrier layer (122) preventing the diffusion of metal elements. The invention also relates to a process for manufacturing a piezoelectric-on-insulator (POI) substrate.

IPC Classes  ?

• H10N 30/00 - Piezoelectric or electrostrictive devices
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/762 - Dielectric regions
• H10N 30/853 - Ceramic compositions