Abstract

An electronic package includes a carrier structure, an optoelectronic module, at least a first transceiver module, a first semiconductor component, and a heat dissipation component. The optoelectronic module is disposed on and electrically connected to the carrier structure, and includes an optoelectronic component and a first encapsulating layer covering the optoelectronic component. The first transceiver module includes a first optical signal transmission unit. The first semiconductor component is disposed on and electrically connected to the carrier structure. The heat dissipation component is connected to the first semiconductor component, and the first transceiver module is coupled to the heat dissipation component. Hence, the number of optical fibers connected to the electronic package can be increased, so the amount of data that can be received and transmitted by the electronic package per unit time can be greatly increased, thereby significantly improving data transmission and processing speed of the electronic package.

IPC Classes  ?

• G02B 6/42 - Coupling light guides with opto-electronic elements
• H01L 23/367 - Cooling facilitated by shape of device
• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits

Abstract

A test apparatus and a test cover thereof are provided for electrical testing of a relay on a carrier board. The test cover includes a sleeve and a plurality of contacts. The sleeve is used to sleeve-couple to the relay. The plurality of contacts are disposed at an end of the sleeve and protrude from the sleeve and are used to contact and be electrically connected to a plurality of pins of the relay when the sleeve is sleeve-coupled to the relay for electrical testing. The test apparatus is capable of performing directly electrical test on the relay on the carrier board without the need for desoldering or dismantling the relay prior to performing electrical test. Therefore, the time required for addressing abnormal events during electronic component testing can be reduced, and the hazards associated with desoldering or dismantling the carrier board can be prevented.

IPC Classes  ?

• G01R 31/327 - Testing of circuit interrupters, switches or circuit-breakers
• G01R 31/00 - Arrangements for testing electric propertiesArrangements for locating electric faultsArrangements for electrical testing characterised by what is being tested not provided for elsewhere

Abstract

An electronic package is provided and includes a first circuit structure having opposite first and second surfaces; an electronic component set including a first electronic component and a second electronic component and having opposite first and second sides, wherein the first electronic component is located on the first side and has opposite first active surface and first inactive surface, the second electronic component has opposite second active surface and second inactive surface, and a part of the second active surface protrudes and is exposed from an outside of the first electronic component to electrically connect to the first surface; and an encapsulating layer defining opposite first encapsulating surface and second encapsulating surface, wherein the second encapsulating surface is connected to the first surface. As such, the overall height of the electronic package can be reduced and the heat dissipation efficiency of the electronic package can be improved also.

IPC Classes  ?

• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices

Abstract

A substrate structure and a manufacturing method thereof are provided, in which a core layer having first and second connection pads is formed, and first bonding pads of a first circuit build-up layer and second bonding pads of a second circuit build-up layer are respectively bonded to the first connection pads and the second connection pads, so that the first circuit build-up layer and the second circuit build-up layer are respectively located on a first side and a second side of the core layer, and a first gap is formed between the first side and the first circuit build-up layer, and a second gap is formed between the second side and the second circuit build-up layer. Thereby, the core layer and the first and second circuit build-up layers can be manufactured separately and concurrently, thereby shortening the manufacturing process of the substrate structure and improving the yield of the substrate structure.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates

Abstract

An electronic package is provided. A plurality of conductive posts with multilayer composite materials and at least one electronic component are disposed on a carrier structure. An encapsulation layer covers the at least one electronic component and the plurality of conductive posts. A circuit structure is disposed on the encapsulation layer and is electrically connected to the plurality of conductive posts. Therefore, the multilayer composite materials for the conductive posts achieve CTE (coefficient of thermal expansion) matching, improve electrical conductivity, and prevent copper diffusion in high temperature or high frequency working environments. A manufacturing method of the electronic package is also provided.

IPC Classes  ?

• H05K 1/02 - Printed circuits Details
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
• H05K 1/14 - Structural association of two or more printed circuits
• H05K 1/18 - Printed circuits structurally associated with non-printed electric components
• H05K 3/34 - Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
• H05K 3/36 - Assembling printed circuits with other printed circuits

Abstract

An electronic package is provided and includes a carrier structure, an electronic component disposed on the carrier structure, a heat dissipation structure disposed on the electronic component via a thermal interface material, a back side metallization formed on the electronic component and connected to the thermal interface material, and a conductive adhesive provided between the thermal interface material and the back side metallization. The surface adhesiveness of the conductive adhesive is used to limit the displacement of the thermal interface material relative to the back side metallization, thereby preventing the displacement of the thermal interface material from causing poor bonding between the heat dissipation structure and the electronic component, which would affect the heat dissipation efficiency of the electronic package.

IPC Classes  ?

• H01L 23/373 - Cooling facilitated by selection of materials for the device
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/367 - Cooling facilitated by shape of device

Abstract

An electronic package and a manufacturing method thereof are provided, in which a first recessed portion and a second recessed portion are respectively formed on a first side and a second side of a core board, a first electronic element and a second electronic element are respectively disposed in the first recessed portion and the second recessed portion, an insulating layer fills the first recessed portion and the second recessed portion to cover the first electronic element and the second electronic element, a circuit layer is formed on the insulating layer, and a plurality of conductive blind vias are formed in the insulating layer and electrically connected to the circuit layer as well as the first and second electronic elements, so that the first electronic element and the second electronic element will not offset when the insulating layer fills the first recessed portion and the second recessed portion.

IPC Classes  ?

• H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

An electronic package and a manufacturing method thereof are provided. The electronic package includes: a package module having a first side, a second side opposite to the first side and a first electronic element disposed on the first side; an antenna module having a first surface, a second surface opposite to the first surface; a second electronic element disposed between the second side of the package module and the first surface of the antenna module, in which the first surface of the antenna module is disposed on the second side of the package module via a plurality of conductive elements; and a covering layer covering the second electronic element, in which the second electronic element and the covering layer are thinned to reduce thickness of the electronic package.

IPC Classes  ?

• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 23/552 - Protection against radiation, e.g. light
• H01Q 1/22 - SupportsMounting means by structural association with other equipment or articles

Abstract

Provided is a package substrate which is manufactured by forming a heterogeneous layer on a board body for forming a circuit structure on the heterogeneous layer, and then removing the board body. Hence, a circuit layer of the circuit structure will not be etched when the heterogeneous layer is subsequently removed. Therefore, solder balls can be effectively bonded to the circuit layer in subsequent processes to avoid a non-wetting issue.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

An electronic package is provided, including a carrier structure, an electronic component disposed on the carrier structure, a heat dissipation structure connected to the electronic component through a thermal interface material, a back side metallization disposed on the electronic component and connected to the thermal interface material, and a liquid metal disposed between the thermal interface material and the back side metallization. A surface viscosity of the liquid metal is used to limit the displacement of the thermal interface material relative to the back side metallization, thereby preventing the heat dissipation structure from being poorly bonding to the electronic component due to misalignment of the thermal interface material, which affects the heat dissipation efficiency of the electronic package.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/36 - Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
• H01L 23/498 - Leads on insulating substrates

Abstract

A semiconductor device and a manufacturing method thereof are provided, which mainly form a first wiring layer, a bottom routing layer, and a plurality of conductive pillars on a carrier structure, and the plurality of conductive pillars are electrically connected to the first wiring layer and the bottom routing layer. Next, an encapsulation layer covering the plurality of conductive pillars is formed on the first wiring layer and the bottom routing layer, wherein the encapsulation layer includes a magnetic material. Then, a top routing layer and a second wiring layer are formed on the encapsulation layer, and the plurality of conductive pillars are electrically connected to the top routing layer and the second wiring layer, wherein the bottom routing layer, the plurality of conductive pillars, and the top routing layer constitute a conductor structure, and the conductor structure and the encapsulation layer confined thereby constitute an inductor module.

IPC Classes  ?

• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials

Abstract

An electronic package and a manufacturing method thereof and an interposer are provided, in which grooves are formed on conductive through holes on a back side of an interposer body of the interposer, and a routing structure electrically connected to the conductive through holes is formed directly on the back side of the interposer body and in the grooves, without a passivation layer to be formed, such that the CVD process and CMP process are omitted, thereby effectively simplifying the manufacturing process and saving a lot of manufacturing time and material costs.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

An electronic package and a manufacturing method thereof are provided, in which a thermoelectric circuit structure and a thermal conductive structure are provided on a wiring structure connected to electronic components. The thermal conductive structure includes a thermal conductive board and thermal conductive pillars, the thermal conductive board and the thermal conductive pillars form interconnected hollow chambers for injecting a working fluid, and one end of each of the thermal conductive pillars is connected to the thermal conductive board, and the other end is connected to the thermoelectric circuit structure to generate a voltage via the temperature difference to drive the working fluid inside the thermal conductive structure to flow, thereby achieving the heat dissipation effect of the electronic package.

IPC Classes  ?

• H01L 23/46 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/36 - Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
• H01L 23/49 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of soldered or bonded constructions wire-like
• H01L 23/498 - Leads on insulating substrates
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
• H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers
• H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
• H10N 10/10 - Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects operating with only the Peltier or Seebeck effects

Abstract

The present disclosure provides an electronic package including: a carrier structure having a circuit layer, a first electronic component disposed on the carrier structure and electrically connected to the circuit layer, and a thermal conductive layer applied to the first electronic component and the carrier structure. The present disclosure replaces the conventional method of using heat sinks by coating a thermal conductive layer such as a metal layer, thereby avoiding problems of the heat sink occupying a position of the carrier structure and the heat sink falling off.

IPC Classes  ?

• H01L 23/367 - Cooling facilitated by shape of device
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

An electronic package including a carrier structure, an electronic component bonded to the carrier structure, a heat conduction component bonded to the electronic component, a substrate, and an encapsulating material. A first surface of the substrate is bonded to an area of the carrier structure surrounding the electronic component. An enclosure is formed around the opening, and the encapsulating material at least encapsulates surroundings of the electronic component and the heat conduction component. The present disclosure can prevent the encapsulant overflowing to the top of the heat conduction component and reducing an area of the heat conduction component contacting air, or overflowing to a top surface of the substrate and covering contacts on the top surface of the substrate. Thereby, failures of the electronic package caused by poor heat dissipation or electrical contact can be avoided to improve reliability of the electronic package.

IPC Classes  ?

• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/367 - Cooling facilitated by shape of device
• H01L 23/498 - Leads on insulating substrates

Abstract

An electronic package and a method for fabrication the same are provided. The method includes: disposing an electronic component on a substrate; forming an encapsulant layer on the substrate to encapsulate the electronic component; and forming a shielding layer made of metal on the encapsulant layer. The shielding layer has an extending portion extending to a lateral side of the substrate along a corner of the encapsulant layer, without extending to a lower side of the substrate. Therefore, the present disclosure prevents the shielding layer from coming into contact with conductive pads disposed on the lower side of the substrate and thereby avoids a short circuit from occurrence.

IPC Classes  ?

• H01L 21/44 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/485 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
• H01L 23/552 - Protection against radiation, e.g. light
• H10D 30/60 - Insulated-gate field-effect transistors [IGFET]
• H10D 84/40 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or with at least one component covered by groups or , e.g. integration of IGFETs with BJTs

Abstract

A separation device is provided and includes: a pin cover having an action platform and an accommodating space for an object to be separated to be placed on the action platform, where the action platform is defined with an active region and an idle region, the active region is provided with a plurality of first apertures, and the plurality of first apertures penetrate through the action platform and communicate with the accommodating space; an ejector pin plate disposed in the accommodating space; a plurality of ejector pins disposed on the ejector pin plate and corresponding to positions of the plurality of first apertures; and a plurality of bumps disposed in the idle region of the action platform, so that the bumps can provide sufficient support for the object to be separated without hindering the separation operation of the ejector pins.

IPC Classes  ?

• H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

Abstract

An electronic component and a manufacturing method thereof are provided, in which a plurality of conductive bumps are covered by a protective layer on a second side of a base material, and then a plurality of the electronic components are bonded on a tape of a carrier via the protective layer thereof, so that the protective layer made of such as water-soluble adhesive can cover each of the conductive bumps, and the protective layer can be removed in a subsequent process. Therefore, even if the distance between the conductive bumps becomes smaller with the requirement for miniaturization so that the tape of the carrier does not cover each of the conductive bumps, the conductive bumps will not have adhesive residue issue, such that the electronic component can be designed to meet miniaturization requirements.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
• H01L 23/498 - Leads on insulating substrates
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

A lead frame is provided and includes: a die pad; and a plurality of connecting pads provided around the die pad, and bottom surfaces of at least a portion of the connecting pads are formed with metallic protective pads, each of the metallic protective pads is defined with a connecting reserved area and a processing area around the connecting reserved area, and the metallic protective pads and the connecting pads are made of different materials. By the implementation of the lead frame, the shape and size of each contact of an electronic package made using the lead frame technology are without errors caused by the different etching rates along a direction perpendicular to a forming direction and along a direction parallel to the forming direction, thereby avoiding problems such as poor contact due to the errors in the shapes and the sizes of the contacts.

IPC Classes  ?

• H01L 23/495 - Lead-frames
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

A semiconductor device with a heat sink is provided, in which a base material is rectangular and provided with heat sink mounting areas at four sides of the base material. An adhesive layer is disposed on the heat sink mounting areas, and the adhesive layer at at least one side forms a first pattern, where a width of the first pattern is tapered from both ends of the side toward a center of the side, and the heat sink is mounted on the base material via the adhesive layer.

IPC Classes  ?

• H01L 23/10 - ContainersSeals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/367 - Cooling facilitated by shape of device

Abstract

A carrier structure is provided and includes: a lower shielding layer including lower shielding areas and a first separation lane; a circuit layer including conductive traces, a grounding block, and second separation lanes whose locations do not correspond to the location of the first separation lane; an upper shielding layer including upper shielding areas and a third separation lane whose location does not correspond to the locations of the second separation lanes; and at least two insulation layers with a plurality of conductive vias formed therein. Therefore, the edges of the separation lanes in the layers of the carrier structure and the electronic package having the same do not correspond to each other in the vertical direction to form structural weakness, thereby preventing cracks from occurring to the outer protective layer or even the entire carrier structure, such that the reliability of the product can be improved.

IPC Classes  ?

• H05K 1/02 - Printed circuits Details

Abstract

An electronic package is provided, in which an electronic element is disposed on an upper side of a circuit structure, a package layer covers the electronic element, and an action structure is embedded in the package layer, so that the action structure is exposed from a surface of the package layer, and then a bonding element is disposed on a lower side of the circuit structure and corresponding to the position of the action structure, so as to form a thermal conduction between the bonding element and the action structure. Therefore, a laser can transfer heat energy to the bonding element via the action structure, so that a solder material on the bonding element can be reflowed.

IPC Classes  ?

• H01L 23/367 - Cooling facilitated by shape of device
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/498 - Leads on insulating substrates
• H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers

Abstract

An electronic package and a manufacturing method thereof are provided. The electronic package at least includes an electronic element, a conductive pillar, a reinforcement member, an encapsulation layer and a redistribution layer. The conductive pillar and the reinforcement member are both disposed around the electronic element. The electronic element, the conductive pillar and the reinforcement member are encapsulating by the encapsulation layer. The redistribution layer is disposed on the same side of the electronic element, the conductive pillar, the reinforcement member and the encapsulation layer, and electrically connected to the electronic element and the conductive pillar. The reinforcement member has high hardness and a tunable coefficient of thermal expansion (CTE), which can enhance the strength and rigidity of the electronic package to reduce the warpage of the electronic package.

IPC Classes  ?

• H01L 23/18 - Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates
• H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers

Abstract

A conductive bump structure is provided, in which a protective layer, an insulating layer, a metal layer, and a metal bump are formed in sequence on a bonding pad of a semiconductor substrate, wherein a thickness and a width of the second area of the insulating layer that is not covered by the metal bump are greater than a thickness and a width of the first area that is covered by the metal bump, respectively. Accordingly, the stress on the semiconductor substrate can be reduced.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

A package substrate is provided, which includes an insulating protective layer formed on a circuit structure, wherein circuit structure includes an insulating layer and a first circuit layer bonded to the insulating layer, and the insulating layer has at least one recessed portion, so that the insulating protective layer is bonded to a bonding layer formed in the recessed portion, or the insulating protective layer is received in the recessed portion and protruded from the recessed portion. Therefore, when the insulating protective layer is designed as NSMD, the portions around the openings will not be disposed on the surface of the insulating layer to avoid excessive undercut structures in the insulating protective layer. Also provided is a manufacturing method for the package substrate.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or

Abstract

An electronic package and a manufacturing method thereof are provided, wherein a circuit structure is formed on a carrier structure having a groove and through holes, a plurality of conductive pillars are disposed in a plurality of through holes to be electrically connected to the circuit structure, and electronic elements are placed in the groove to be electrically connected to the circuit structure, then a wiring structure is disposed on the carrier structure to be electrically connected to the plurality of conductive pillars, and wherein the carrier structure is a plate made of semiconductor material, thereby the manufacturing process can be simplified and the warpage problems can be reduced.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H05K 1/18 - Printed circuits structurally associated with non-printed electric components
• H05K 3/46 - Manufacturing multi-layer circuits

Abstract

A positioning device for chip, which includes: a carrying unit having a recess for accommodating and fixing a chip; a detection unit used to detect whether the chip is correctly placed in the recess; and a vibration positioning unit signally connected to the detection unit and mechanically connected to the carrying unit. When the detection unit detects that the chip is not correctly placed in the recess, the detection unit sends a trigger signal to drive the vibration positioning unit to vibrate the carrying unit to correctly place the chip in the recess, and vibration parameters of the vibration positioning unit correspond to physical specifications of the chip. By the implementation of the present disclosure, the chip can be correctly positioned and accommodated in the carrying unit, so as to avoid process delays or even defects caused by chip position deviation or mispositioning, thereby improving the process speed and yield.

IPC Classes  ?

• G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
• G01M 7/02 - Vibration-testing
• H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
• H01L 21/68 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for positioning, orientation or alignment

Abstract

An electronic package is provided. The electronic package includes an encapsulating layer encapsulating a plurality of conductive pillars and an interposer board that has through-silicon vias. An electronic component is disposed on the encapsulating layer and electrically connected to the conductive pillars and the through-silicon vias. The conductive pillars act as an electric transmission path of a portion of electric functions of the electronic component. Therefore, the number of the through-silicon vias is reduced, and the fabrication time and chemical agent cost are reduced. Also, the through silicon interposer of a large area can be replaced by a smaller one, and the yield is increased. Further, a method of fabricating an electronic package is provided.

IPC Classes  ?

• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates

Abstract

The present disclosure provides an electronic package having an electronic module, an optoelectronic component disposed on and electrically connected to the electronic module, and a lens module disposed on a side of the optoelectronic component. By the implementation of the present disclosure, the electronic package can be used with a laser without the need to provide a shelf for supporting and fixing an optical fiber. Therefore, the structure and manufacturing process of the electronic package can be effectively simplified, thereby improving the yield and the speed of manufacturing and reducing the manufacturing costs.

IPC Classes  ?

• H01L 27/144 - Devices controlled by radiation
• G02B 6/42 - Coupling light guides with opto-electronic elements
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/49 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of soldered or bonded constructions wire-like
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers

Abstract

An antenna substrate, electronic package and manufacturing method thereof are provided in which an antenna substrate including a silicon core layer, a circuit structure and conductive pillars, and the circuit structure has a first dielectric layer, a first circuit layer and a first antenna portion. The circuit structure and the conductive pillars are formed on opposite sides of the silicon core layer, and the antenna substrate is stacked and bonded to a circuit board having a second antenna portion through the conductive pillars. Thereby, the present disclosure can thin a thickness of the antenna substrate and the electronic package, or precisely control a distance between the antenna substrate and the circuit board.

IPC Classes  ?

• H01Q 9/04 - Resonant antennas
• H01Q 1/38 - Structural form of radiating elements, e.g. cone, spiral, umbrella formed by a conductive layer on an insulating support
• H01Q 1/42 - Housings not intimately mechanically associated with radiating elements, e.g. radome
• H01Q 21/06 - Arrays of individually energised antenna units similarly polarised and spaced apart

Abstract

Provided are an electronic package and a manufacturing method thereof, including an electronic module disposed on a first surface of a carrier structure, a retaining wall structure mounted on the first surface of and positioned an outside the electronic module with a predetermined distance. A heat dissipation material is formed to cover the electronic module and be positioned between the retaining wall structure and the electronic module. The heat dissipation material formed between the retaining wall structure and the electronic module is with a predetermined thickness. A heat dissipation structure is disposed on the heat dissipation material and the retaining wall structure, and a fluid regulation space is formed between the heat dissipation structure, the heat dissipation material and the retaining wall structure, and is communicated with at least a vent formed in the heat dissipation structure for heat dissipation.

IPC Classes  ?

• H01L 23/373 - Cooling facilitated by selection of materials for the device
• H01L 23/367 - Cooling facilitated by shape of device

Abstract

An electronic structure is provided, in which a plurality of conductors are disposed on one surface of an electronic body, an epoxy molding compound is used as a protective layer to encapsulate the plurality of conductors, a circuit portion is bonded onto the other surface of the electronic body, and a plurality of external bumps and solder material are formed on the circuit portion. Therefore, with the design of the protective layer, heat energy can be effectively transferred from the protective layer to the solder material below during a process of heating the electronic structure so as to avoid a problem of non-wetting of the solder material.

IPC Classes  ?

• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/498 - Leads on insulating substrates
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 1/18 - Printed circuits structurally associated with non-printed electric components
• H05K 3/46 - Manufacturing multi-layer circuits

Abstract

Provided are an electronic package and a manufacturing method thereof. An electronic component is embedded in an encapsulation layer, the electronic component has a first electrode pad and a second electrode pad on two opposite sides thereof to form a double-sided power supply structure, and thus a circuit structure and a wiring structure on the two opposite sides of the electronic component can be electrically connected to the first electrode pad and the second electrode pad, thereby it is beneficial for reducing loss of the power.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement

Abstract

An electronic package is provided, which includes: a packaging module having a first side, a second side opposite to the first side, and a first electronic element provided on the first side; an antenna module having a first surface and a second surface opposite to the first surface, wherein the first surface of the antenna module is coupled to the second side of the packaging module via a plurality of conductive elements; and a second electronic element disposed between the second side of the packaging module and the first surface of the antenna module. Also provided is a method of manufacturing the electronic package.

IPC Classes  ?

• H01Q 1/22 - SupportsMounting means by structural association with other equipment or articles
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 23/552 - Protection against radiation, e.g. light
• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
• H01Q 9/04 - Resonant antennas
• H01Q 21/06 - Arrays of individually energised antenna units similarly polarised and spaced apart

Abstract

An electronic package and a manufacturing method thereof are provided, in which an electronic element and an interposer plate are provided on a carrier structure, so that the interposer plate covers the electronic element, wherein the interposer plate is formed with an opening such that the electronic element is exposed from the opening, and a thermal conductive block contacting the electronic element is placed in the opening to provide a heat dissipation path for the electronic element via the thermal conductive block.

IPC Classes  ?

• H01L 23/373 - Cooling facilitated by selection of materials for the device
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
• H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers

Abstract

An electronic package includes a first electronic component having a first active surface disposed in a first encapsulating layer; at least one second electronic component having a second active surface disposed in a second encapsulating layer; and an active electronic component having a third active surface disposed in a third encapsulating layer, the third active surface is electrically connected to and facing to the first active surface and the second active surface respectively, and the third active surface is directly electrically connected to the first active surface. By the implementation of the present invention, the signal transmission speed in the package can be accelerated by directly electrically connecting the active electronic component to the first electronic component disposed in the third and the first encapsulating layers respectively, and the work processing speed can be accelerated by assistant provided by the first electronic component.

IPC Classes  ?

• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
• H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass

Abstract

An electronic package and a manufacturing method thereof are provided. The electronic package includes a photonic component, an electronic component and an optical component. The photonic component has a first surface and a second surface opposite thereto, and the first surface is defined with an electrical bonding region and an optical coupling region that are non-overlapping with each other. The electronic component is disposed on the electrical bonding region and is electrically connected to the photonic component. The optical component is disposed on the optical coupling region and is optically connected to the photonic component. The above-mentioned electronic package and manufacturing method thereof employ a 2.5-dimensional stack structure for coupling the optical component without forming a cantilever structure. Therefore, the present disclosure achieves the advantages of high heat dissipation efficiency, simplified manufacturing process, higher yield and shorter process cycle.

IPC Classes  ?

• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/495 - Lead-frames
• H01L 23/498 - Leads on insulating substrates

Abstract

An electronic package is provided, including a carrier structure; a packaging module disposed on one side of the carrier structure and including an encapsulation layer, an electronic component, a circuit structure, and a wiring structure, wherein the encapsulation layer has a first surface and a second surface opposing the first surface, the electronic component is embedded in the encapsulation layer, the circuit structure is formed on the second surface of the encapsulation layer and electronically connected to the electronic component, and the wiring structure is formed on the first surface of the encapsulation layer and electronically connected to the electronic component; and a heat dissipation structure formed on the circuit structure of the packaging module. A manufacturing method of an electronic package is further provided.

IPC Classes  ?

• H01L 23/367 - Cooling facilitated by shape of device
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/10 - ContainersSeals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/373 - Cooling facilitated by selection of materials for the device
• H01L 23/498 - Leads on insulating substrates

Abstract

A detection equipment and a detection method for detecting whether a semiconductor device is provided with a patch, wherein multiple light sources are used to perform color analysis and sampling of the patch via a color sensor, so as to identify the patch by using a proportion of light and color components reflected by the patch, and a control device is used to receive an activation signal of the color sensor and generating a detection value, wherein if the detection value is greater than a preset value, it is determined that the semiconductor device is provided with a patch, and wherein if the detection value is less than the preset value, it is determined that the semiconductor device is not provided with a patch.

IPC Classes  ?

• H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
• G01J 3/50 - Measurement of colourColour measuring devices, e.g. colorimeters using electric radiation detectors
• H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations

Abstract

An electronic package is provided, in which a mesh structure is disposed between a circuit structure and an electronic element to increase the shunt path of current. Therefore, when the electronic element is used as an electrode pad of a power contact, the current can be passed through a conductive sheet of the circuit structure via the mesh structure, such that the power loss can be reduced and the IR drop of the electronic element can meet the requirements.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement

Abstract

An electronic package is provided, in which a plurality of antenna structures and a heat sink are integrated on a package module including an electronic element, so as to guide the heat energy generated by the electronic element out of the package module via the heat sink. Therefore, when the electronic package is configured with the plurality of antenna structures, the heat dissipation of the electronic element can be improved.

IPC Classes  ?

• H01L 23/66 - High-frequency adaptations
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/367 - Cooling facilitated by shape of device
• H01L 23/373 - Cooling facilitated by selection of materials for the device
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01Q 1/22 - SupportsMounting means by structural association with other equipment or articles

Abstract

An electronic package is provided and includes an electronic structure and a plurality of conductive pillars embedded in a cladding layer, a circuit structure formed on the cladding layer, and a reinforcing member bonded to a side surface of the cladding layer, where a plurality of electronic elements are disposed on and electrically connected to the circuit structure, such that the electronic structure electrically bridges any two of the electronic elements via the circuit structure, so as to enhance the structural strength of the electronic package and avoid warpage by means of the design of the reinforcing member.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/498 - Leads on insulating substrates
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers

Abstract

Provided is an electronic package including a carrier structure and a packaging module disposed on the carrier structure by a plurality of conductive members. The packaging module includes a plurality of circuit layers and a plurality of conductive vias, wherein the plurality of conductive vias are electrically connected to two of the circuit layers respectively, and a central axis of each of the conductive vias is deviated from a central axis of each of the conductive members. By the implementation of the present disclosure, the stresses or the external forces exerted on the conductive members can be prevented from being directly transferred to the conductive vias which would otherwise cause the conductive vias to tilt or even the electronic package to fail, such that the reliability of the electronic package can be enhanced.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

An electronic package and a manufacturing method thereof are provided, in which an electronic element and a packaging layer encapsulating around the electronic element are disposed on a carrier structure, and the carrier structure is connected to a substrate through a plurality of solder bumps, and the electronic element is exposed by a thermal uniform interposer covering the packaging layer to irradiate the electronic element and the thermal uniform interposer with a laser beam, so that the energy of the laser beam absorbed by the thermal uniform interposer is converted into radiative heat, which is transmitted to the packaging layer below via the air, so that the solder bumps can be uniformly heated to avoid the problem of non-wetting of the solder from occurrence.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates

Abstract

A manufacturing method of an electronic package is provided, which includes: adhering a packaging module to a surface of a carrier through a first adhesive layer, in which the packaging module has a plurality of packaging units jointly defined by first and second cutting paths; performing a pre-cutting process to cut along each of the first cutting paths; disposing at least one reinforcement structure on the surface of the first adhesive layer; adhering a plurality of optoelectronic components to the packaging units through a second adhesive layer; electrically connecting each of the optoelectronic components to a corresponding one of the packaging units; performing a singulation process to cut down the packaging module along the second cutting paths; and removing the reinforcing structure, the first adhesive layer and the carrier to form a plurality of the electronic packages.

IPC Classes  ?

• H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
• H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices

Abstract

A conductive bump structure and a manufacturing method thereof are provided. A first insulating layer is formed on a semiconductor substrate having bonding pads and a protective layer, and the first insulating layer has first openings and second openings, so that the bonding pads are exposed from the first openings, and portions of the protective layer are exposed from the second openings. A metal layer electrically connected to the bonding pads is formed on the first insulating layer. A second insulating layer is formed on the first insulating layer and the metal layer. The second insulating layer has third openings corresponding to positions of the second openings, so each of the second openings and each of the third openings together form a groove structure. A conductive metal layer electrically connected to the metal layer is formed in the groove structure. Metal bumps are formed on the conductive metal layer.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
• H01L 23/15 - Ceramic or glass substrates
• H01L 23/498 - Leads on insulating substrates

Abstract

A manufacturing method of an electronic package is provided, which includes: disposing an electronic element and a heat dissipation structure on a carrier structure, wherein the heat dissipation structure is disposed on the electronic element by a heat conductor, and a flux material is sandwiched between the heat conductor and the heat dissipation structure and between the heat conductor and the electronic element; performing a first heating operation at a first temperature to vaporize the flux material; and performing a second heating operation at a second temperature to melt the heat conductor, and forming inter-metallic compound layers between the heat conductor and the heat dissipation structure and between the heat conductor and the electronic element.

IPC Classes  ?

• H01L 23/367 - Cooling facilitated by shape of device
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/373 - Cooling facilitated by selection of materials for the device

Abstract

A method for fabricating an electronic package is provided, which mainly provides a first carrier structure on which a plurality of packaging structures are disposed and a cutting path is provided between each of the packaging structures, wherein each of the packaging structures has a circuit structure disposed on the first carrier structure, an electronic component disposed on the circuit structure, an encapsulating layer disposed the circuit structure and encapsulating the electronic component, and a routing structure disposed on the encapsulating layer; a pre-cutting process is performed to remove the routing structure and encapsulating layer above the cutting path to reduce warpage phenomenon, thereby avoiding yield problems in the subsequent process; and a second carrier structure is bonded onto the routing structure and the first carrier structure is removed.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices

Abstract

Provided is an electronic package, in which a heat dissipating body is formed on an electronic device and is combined with a heat sink so that the electronic device, the heat dissipating body and the heat sink form a receiving space, and a heat dissipating material is formed in the receiving space and in contact with the heat sink and the electronic device, where a fluid regulating space is formed between the heat dissipating material and the heat dissipating body and is used as a volume regulating space for the heat dissipating material during thermal expansion and contraction.

IPC Classes  ?

• H01L 23/367 - Cooling facilitated by shape of device
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/373 - Cooling facilitated by selection of materials for the device
• H01L 23/42 - Fillings or auxiliary members in containers selected or arranged to facilitate heating or cooling

Abstract

An electronic package and a manufacturing method thereof are provided, in which a wiring structure electrically connected to a photonic structure is disposed on a surface of a part of the photonic structure, an electronic component is disposed on the wiring structure to be electrically connected to the wiring structure, and an optical element is disposed on a surface of another part of the photonic structure to be electrically connected to the photonic structure. Therefore, the photonic structure and the electronic component are placed relatively vertically on opposite sides of the wiring structure, thereby effectively reducing the layout area of the wiring structure to meet the demand for miniaturization.

IPC Classes  ?

• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 23/498 - Leads on insulating substrates

Abstract

An electronic package is provided, which comprises: a carrier structure; an electronic element disposed on and electrically connected to the carrier structure; a supporting structure disposed on the carrier structure; a semiconductor element disposed on the carrier structure; and an optoelectronic element disposed on, electrically connected to the semiconductor element and partially supported by the supporting structure. By the implementation of the present disclosure, the optoelectronic element in the electronic package and/or the optical fiber connected to the electronic package can obtain a well and firm support, avoiding the breakage of the optoelectronic element and/or the optical fiber, so as to improve the manufacturing yield, the reliability and the service life of the electronic package.

IPC Classes  ?

• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
• G02B 6/42 - Coupling light guides with opto-electronic elements
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices

Abstract

An electronic package and a manufacturing method thereof are provided, in which a first carrier structure and a second carrier structure with a thickness less than that of the first carrier structure are provided, at least a first electronic component is disposed on the first carrier structure, and at least a second electronic component is disposed on the second carrier structure, wherein the first electronic component and the second electronic component are covered by an encapsulating layer, such that the second electronic component can be disposed on the second carrier structure by using a packaging module to avoid excessive height of the packaging module from occurrence.

IPC Classes  ?

• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates
• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits

Abstract

The present disclosure provides a circuit structure having an insulating layer; a plurality of first circuits disposed on one side of the insulating layer; and a plurality of first electrical connection pads, each having a first extension portion extending toward and electrically connected to one end of a first circuit of the first circuits, wherein a width of the extension portion gradually decreases toward a junction of the first extension portion and the first circuit. By implementing of the present disclosure, stress on the junction between the electrical connection pad and the circuit can be dispersed along the extension portion through the arrangement of the extension portion and its tapered width design, thereby preventing fracture on the junction of the electrical connection pad and the circuit due to excessively concentrated stress, so that the manufacturing yield and reliability of semiconductor packages with this circuit structure can be improved.

IPC Classes  ?

• H01L 23/528 - Layout of the interconnection structure
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

Abstract

A test equipment is provided, which includes a cabin for providing a low-temperature testing environment for elements under test, and an air curtain structure surrounding the cabin to send dry air toward the cabin. The air curtain structure includes a ring body and a plurality of openings disposedinside the ring body, so that the ring body can send dry air toward the cabin through the plurality of openings, thereby reducing the ambient humidity and preventing condensation water dripping from causing the test equipment damage.

IPC Classes  ?

• G01N 17/00 - Investigating resistance of materials to the weather, to corrosion or to light
• F24F 9/00 - Use of air currents for screening, e.g. air curtains

Abstract

An electronic package and the manufacturing method thereof are provided. The method includes forming a circuit structure on an encapsulating structure with a recess and a plurality of vias, disposing a plurality of conductive pillars in the plurality of vias to be electrically connected to the circuit structure, and disposing an electronic component in the recess to be electrically connected to the circuit structure. Afterwards, a routing structure is disposed on the encapsulating structure to be electrically connected to the plurality of conductive pillars and the electronic component. Therefore, by disposing the electronic component in the recess, the encapsulating structure covers the electronic component to facilitate dissipation of thermal stress.

IPC Classes  ?

• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
• H01L 23/498 - Leads on insulating substrates

Abstract

An electronic package is provided, in which a circuit board and a circuit block are embedded in an encapsulating layer at a distance to each other, and circuit structures are formed on the two opposite surfaces of the encapsulating layer with electronic components arranged on one of the circuit structures. The circuit block and the circuit board embedded in the encapsulating layer are spaced apart from each other to allow to separate current conduction paths. As such, the circuit board will not overheat, and issues associated with warpage of the circuit board can be eliminated. Moreover, by embedding the circuit block and the circuit board in the encapsulating layer at a distance to each other, the structural strength of the encapsulating layer can be improved.

IPC Classes  ?

• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/498 - Leads on insulating substrates

Abstract

An electronic package is provided and includes a substrate structure, an electronic element disposed on the substrate structure and an encapsulation layer encapsulating the electronic element, where at least one functional circuit is formed on a surface of a substrate body of the substrate structure, and a wire having a smaller width is arranged on a boundary line at a junction between an encapsulation area and a peripheral area, so that when a mold for forming the encapsulation layer is formed to cover the substrate structure, the mold will create a gap around the wire to serve as an exhaust passage. Therefore, when the encapsulation layer is formed, the exhaust passage can be used to exhaust air, so as to avoid problems such as the occurrence of voids or overflows of the encapsulation layer.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement

Abstract

An electronic package and a manufacturing method thereof are provided, in which a plurality of conductive pillars with detachable blocks and a first electronic component with detachable blocks are provided, and the first electronic component, the plurality of detachable blocks and the plurality of conductive pillars are covered with an encapsulating layer, so that the plurality of detachable blocks are exposed from the surface of the encapsulating layer, and then the plurality of detachable blocks are removed to form a plurality of recesses on the surface of the encapsulating layer, so that the plurality of conductive pillars and the first electronic component are exposed from the recesses. Therefore, through the design of the recesses, the contact area between the circuit portion subsequently formed on the encapsulating layer and the encapsulating layer can be increased, thereby preventing from peeling of the circuit portion during thermal cycles.

IPC Classes  ?

• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/498 - Leads on insulating substrates

Abstract

An electronic package and a method for fabricating the same are provided. The electronic package includes a cladding layer embedded with a first electronic component and a plurality of conductive pillars; a circuit structure provided on one surface of the cladding layer; a second electronic component disposed on the circuit structure; an insulating layer disposed on another surface of the cladding layer; and a circuit portion disposed on the insulating layer. It can adjust the deformation of the electronic package by changing the diametric sizes of the plurality of conductive pillars.

IPC Classes  ?

• H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

The present disclosure discloses an electronic package and a manufacturing method thereof. An electronic component is disposed on a substrate, an encapsulation layer covers the electronic component, and a frame that is not in contact with the substrate is embedded in the encapsulation layer, thereby preventing the electronic package from warping by the frame resisting thermal stress.

IPC Classes  ?

• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/495 - Lead-frames

Abstract

An electronic package and a manufacturing method thereof are provided, in which an electronic element and a heat dissipation structure covering the electronic element are disposed on a carrier structure, and the electronic element is covered with a cladding layer. The heat dissipation structure has convex portions facing the carrier structure, so that the bonding area between the heat dissipation structure and the cladding layer is increased via the convex portions, thereby preventing the problem of peeling from occurring to the heat dissipation structure.

IPC Classes  ?

• H01L 23/367 - Cooling facilitated by shape of device
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates

Abstract

An electronic package and a manufacturing method thereof are provided, in which a passive element and an interposer structure are disposed on a carrier structure, the passive element is encapsulated by an encapsulation layer, and the electronic element is disposed on and electrically connected to the passive element and the interposer structure. Therefore, by the design of the electronic element electrically connecting to the passive element, the power transmission path is shortened and the resistance is reduced, thereby achieving the effect of reducing power loss.

IPC Classes  ?

• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/04 - ContainersSeals characterised by the shape
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates

Abstract

An electronic package and manufacturing method are provided. The electronic package includes a carrier structure and an electronic element. The carrier structure has a first side and a second side opposing the first side and includes at least one insulation layer and at least one circuit layer bonded to the at least one insulation layer. The electronic element is disposed on the first side of the carrier structure. A portion of each of the circuit layers of the carrier structure in a response region below the electronic element is hollowed out to reduce signal interference during high frequency signal transmission and to enhance the reliability of high frequency transmission.

IPC Classes  ?

• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/498 - Leads on insulating substrates
• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits

Abstract

An electronic structure is provided and includes: an electronic body having a first surface and a second surface opposing the first surface; a plurality of conductive bumps disposed on the first surface of the electronic body; a protective layer formed on the first surface of the electronic body and covering the plurality of conductive bumps; and a plurality of grooves formed in the protective layer. A manufacturing method of the electronic structure, and an electronic package and a manufacturing method thereof are further provided.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/498 - Leads on insulating substrates
• H01L 23/528 - Layout of the interconnection structure

Abstract

Provided are a conductive bump and its fabricating method, including: forming a first metal layer, a second metal layer, a barrier metal layer, and a third metal layer on a bonding pad of a semiconductor substrate in sequence. The first metal layer is a copper layer, the second metal layer is a nickel layer, the barrier metal layer is a copper layer, and the third metal layer is a tin-silver alloy layer. The metal migration problem can be prevented by adding the barrier metal layer between the third metal layer and the second metal layer.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

An electronic package and a manufacturing method thereof are provided, in which at least one groove and a plurality of openings are formed on a first side of a carrier member, a plurality of conductive pillars are formed in the plurality of openings, a first electronic element is accommodated in the groove, a plurality of conductive elements are formed on a second side of the carrier member and electrically connected to the plurality of conductive pillars and the first electronic element, and a circuit structure is formed on the first side of the carrier member and electrically connected to the plurality of conductive pillars and the first electronic element. Therefore, a board body made of semiconductor material serves as the carrier member, so that the coefficient of thermal expansion (CTE) of the carrier member matches the CTE of the first electronic element, which is beneficial to dispersing thermal stress.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers

Abstract

A heat dissipation structure is provided and includes: bonding portions disposed on electronic elements on an electronic carrier board of a test apparatus; and a board body having a first side and a second side opposing the first side, and the board body is disposed on the bonding portions via the first side and formed with heat transfer members on the second side.

IPC Classes  ?

• H05K 7/20 - Modifications to facilitate cooling, ventilating, or heating
• G01R 1/04 - HousingsSupporting membersArrangements of terminals

Abstract

An electronic package is provided, in which a package module is disposed on a first surface of a carrier structure, and the package module is covered by a shielding layer, so that the shielding layer is formed on one part of a side surface of the carrier structure without being formed on the other part of the side surface, and thus a second surface of the carrier structure can be used as an antenna transmitting surface and/or an antenna receiving surface to prevent the shielding layer from interfering with the reception and the transmission of the carrier structure.

IPC Classes  ?

• H01L 23/66 - High-frequency adaptations
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates
• H01L 23/552 - Protection against radiation, e.g. light
• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits

Abstract

An electronic package and a substrate structure thereof are provided, in which an electronic element is disposed on the substrate structure having a circuit layer, and an insulating protective layer of the substrate structure has an opening that exposes the circuit layer. A plurality of extension portions protruding toward the inside of the opening and spaced apart are formed on the edge of the opening of the insulating protective layer, so that when an underfill material is filled into a space between the electronic element and the substrate structure, the space between the electronic element and the substrate structure can be evenly filled up to prevent the underfill material from forming voids.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/498 - Leads on insulating substrates

Abstract

An electronic package in which at least one magnetically permeable member is disposed between a carrier and an electronic component, where the electronic component has a first conductive layer, and the carrier has a second conductive layer, such that the magnetically permeable element is located between the first conductive layer and the second conductive layer. Moreover, a plurality of conductive bumps that electrically connect the first conductive layer and the second conductive layer are arranged between the electronic component and the carrier to surround the magnetically permeable member for generating magnetic flux.

IPC Classes  ?

• H01L 23/64 - Impedance arrangements
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates
• H10D 1/20 - Inductors

Abstract

An electrical detection method provides a wiring structure including a base material body and a plurality of contact portions bonded to the base material body. Each of the contact portions includes an electrical detection pad exposed from a surface of the base material body, an electrical auxiliary pad exposed from the surface of the base material body, and a conductor that electrically connects the electrical detection pad and the electrical auxiliary pad. When probes of a detection device are connected to the contact portions, each of the probes exerts a force on the electrical detection pad and the electrical auxiliary pad of each of the contact portions at the same time, so that the contact force between the probes and the contact portions is enhanced to facilitate the electrical testing.

IPC Classes  ?

• G01R 1/073 - Multiple probes
• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

An electronic package and a manufacturing method thereof are provided, in which a plurality of photonic integrated circuit chips and an auxiliary electronic element are separately configured on a package module to shorten the transmission distance of the optical signal. Therefore, the signal transmission rate of a circuit structure can be increased, thereby improving the overall operating performance of the electronic package.

IPC Classes  ?

• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/367 - Cooling facilitated by shape of device
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or

Abstract

An electronic package and a manufacturing method thereof are provided, in which an electronic module including a carrier structure, at least one first electronic element disposed on a first side of the carrier structure, at least one second electronic element disposed on a second side of the carrier structure, and a plurality of conductive elements is stacked on a substrate via the plurality of conductive elements and a substrate frame, so as to increase an accommodation space between the electronic module and the substrate, thereby preventing the at least one second electronic element of the electronic module from colliding with the substrate.

IPC Classes  ?

• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates

Abstract

A wafer dicing method is provided, which includes: using a laser beam to perform a first dicing on a wafer to form a dicing lane on the wafer; using a bevel knife of a dicing machine to perform a second dicing in an inactive area of the wafer, wherein, before the second dicing, the bevel knife is raised to compensate for a thickness difference of the wafer in the inactive area and the dicing lane; and using the bevel knife to perform a third dicing in the dicing lane, wherein, during the third dicing, a wafer cut width of the second dicing is used to activate a Z-axis compensation mechanism of the dicing machine, so that the bevel knife cuts to a predetermined wafer cut width. As such, the applicable dicing lane width range of the bevel knife is increased via the precise control of the wafer cut width.

IPC Classes  ?

• H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
• H01L 21/268 - Bombardment with wave or particle radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation

Abstract

An electronic package and a manufacturing method thereof are provided, in which an electronic structure is tightly bonded to a carrier structure via a bonding layer, and the bonding layer includes a first bonding material and a second bonding material adjacent to the first bonding material, so that the second bonding material can fill in a deformation place of the first bonding material to ensure that no void is formed between the bonding layer and the carrier structure after the bonding layer is bonded to the carrier structure.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 23/49 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of soldered or bonded constructions wire-like
• H01L 23/498 - Leads on insulating substrates
• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits

Abstract

An electronic package and a manufacturing method thereof are provided, in which an electronic element is disposed on a carrier structure, and the electronic element is encapsulated by a heat dissipation covering layer, and the heat dissipation covering layer is in contact with a metal layer formed on a side surface of the carrier structure, so that heat around the electronic element can be dissipated quickly to effectively avoid a problem of failure of the electronic element due to overheating during operation.

IPC Classes  ?

• H01L 23/367 - Cooling facilitated by shape of device
• H01L 23/373 - Cooling facilitated by selection of materials for the device
• H01L 23/498 - Leads on insulating substrates

Abstract

An electronic package and a manufacturing method thereof are provided, in which a photonic integrated circuit chip and an electronic integrated circuit chip are disposed on opposite sides of an interposer respectively, and the photonic integrated circuit chip and the electronic integrated circuit chip can accomplish signal connection with each other via a plurality of conductive vias in the interposer directly, thereby reducing the power consumption and transmission delay of the signals transmitted between the circuits.

IPC Classes  ?

• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/367 - Cooling facilitated by shape of device
• H01L 23/498 - Leads on insulating substrates
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices

Abstract

An electronic package and a manufacturing method thereof are provided, in which at least one first electronic element, at least one second electronic element and an optical engine module are all disposed or heterogeneously integrated on a first circuit structure and are electrically connected to the first circuit structure. Furthermore, the first circuit structure is disposed on a carrier structure, so that the first circuit structure and the first electronic element, the second electronic element and the optical engine module on the first circuit structure are carried by the carrier structure, and the first electronic element, the second electronic element and the optical engine module are all electrically connected to the carrier structure via the first circuit structure. Therefore, the electronic package can improve data transmission performance, reduce insertion loss/power loss, or reduce the warpage problem.

IPC Classes  ?

• G02B 6/42 - Coupling light guides with opto-electronic elements

Abstract

An electronic package is formed by disposing an electronic element and a lead frame having a plurality of conductive posts on a carrier structure having an antenna function, and encapsulating the electronic element and the lead frame with an encapsulant. The encapsulant is defined with a first encapsulating portion and a second encapsulating portion lower than the first encapsulating portion. The electronic element is positioned in the first encapsulating portion, and the plurality of conductive posts are positioned in the second encapsulating portion. End surfaces of the plurality of conductive posts are exposed from a surface of the second encapsulating portion so as to be electrically connected to a connector.

IPC Classes  ?

• H01L 23/66 - High-frequency adaptations
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates
• H01L 23/552 - Protection against radiation, e.g. light

Abstract

A package substrate and a fabricating method thereof are provided, in which a core board body is provided, a first organic conductive layer and a second metal layer are sequentially formed on a first metal layer of the core board body, and portions of the first organic conductive layer and the first metal layer are removed respectively according to a pattern of the second metal layer, such that the second metal layer, or the second metal layer, the first organic conductive layer and the first metal layer are served as a first circuit layer. Therefore, the design of the organic conductive layer can facilitate the control of the side etching amount of the metal circuit during etching, enabling the production of circuit layer with fine line width/fine line pitch.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
• H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties

Abstract

A substrate structure and a manufacturing method thereof are provided, in which a substrate body including a dielectric layer and a circuit layer formed on the dielectric layer is provided with a first insulating layer thereon, and a second insulating layer is further provided on the first insulating layer, and a mark is arranged on the second insulating layer. In this way, the arrangement of the mark will not affect wiring space of the circuit layer of the substrate body, and it will not be interfered by the circuit layer when reading the mark, thereby improving the reading success rate.

IPC Classes  ?

• H05K 1/02 - Printed circuits Details
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/498 - Leads on insulating substrates
• H05K 1/18 - Printed circuits structurally associated with non-printed electric components

Abstract

An electronic package is provided and includes: a carrier structure, an electronic component disposed on the carrier structure, a heat dissipation structure disposed on the electronic component, a heat conductor sandwiched between the electronic component and the heat dissipation structure, a first intermetallic compound layer formed between the heat dissipation structure and the heat conductor, and a second intermetallic compound layer formed between the heat conductor and the electronic component. Therefore, stable connections can be formed between the heat dissipation structure, the heat conductor and the electronic component via the first intermetallic compound layer and the second intermetallic compound layer to improve heat dissipation effect.

IPC Classes  ?

• H01L 23/367 - Cooling facilitated by shape of device
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/373 - Cooling facilitated by selection of materials for the device
• H01L 23/498 - Leads on insulating substrates

Abstract

An electronic package and a manufacturing method thereof are provided, in which a groove space for accommodating an electronic element is formed on a wiring structure, and an encapsulation layer is formed on the wiring structure to cover the electronic element. Via the design of the groove space, the overall thickness of the electronic package can be easily thinned to meet the demand for miniaturization.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

Provided is an electronic package, in which a conductive structure and an encapsulation layer covering the conductive structure are arranged on one side of a carrier structure having a circuit layer, and an electronic component is arranged on the other side of the carrier structure. The rigidity of the carrier structure is increased by the encapsulation layer, and problems such as warpage or wavy deformations caused by increasing the volume of the electronic package due to functional requirements can be eliminated.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

A carrying structure is provided and is defined with a main area and a peripheral area adjacent to the main area, where a plurality of packaging substrates are disposed in the main area in an array manner, a plurality of positioning holes are disposed in the peripheral area, and a plurality of positioning traces are formed along a part of the edges of the plurality of positioning holes, such that the plurality of positioning traces are formed with notches. Therefore, a plurality of positioning pins on the machine can be easily aligned and inserted into the plurality of positioning holes by the design of the plurality of positioning traces.

IPC Classes  ?

• H05K 1/02 - Printed circuits Details
• H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
• H05K 3/00 - Apparatus or processes for manufacturing printed circuits

Abstract

A chip carrier structure is provided and defined with a chip carrier region and a wire bonding region, and the chip carrier structure includes: an insulating layer; a circuit layer formed on the insulating layer; a solder mask layer formed on the insulating layer and the circuit layer and having a plurality of openings in the wire bonding region; and a protective layer formed on a portion of the circuit layer exposed from the solder mask layer, where an area of the protective layer in each of the openings is less than 70000 μm2. By reducing the areas of the circuit layer exposed from the openings and the protective layer exposed from the openings, the problem of delamination caused by poor bonding force between the materials of the protective layer and the circuit layer is greatly reduced, thereby improving the reliability and lifespan of the chip carrier structure.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates

Abstract

A device and method for controlling air purge equipment are provided, which are applicable to controlling an air purge equipment of a testing system. The testing system tests an object to verify the quality thereof. The air purge equipment reduces the internal humidity of the testing system. The device and method for controlling air purge equipment sense a base temperature of the testing system, and sense whether there is a testing element for testing the object in the testing system, and then automatically turn on or turn off the air purge equipment according to the base temperature and the presence of the testing element, so as to avoid that the low temperature causes the moisture to condense into water and consequently affects the testing of the object, and so as to eliminate unnecessary activation of the air purge equipment to avoid accumulating particles or blowing off the object.

IPC Classes  ?

• G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

Abstract

An electronic package is provided and includes a first circuit structure having opposite first and second surfaces; an electronic component set including a first electronic component and a second electronic component and having opposite first and second sides, wherein the first electronic component is located on the first side and has opposite first active surface and first inactive surface, the second electronic component has opposite second active surface and second inactive surface, and a part of the second active surface protrudes and is exposed from an outside of the first electronic component to electrically connect to the first surface; and an encapsulating layer defining opposite first encapsulating surface and second encapsulating surface, wherein the second encapsulating surface is connected to the first surface. As such, the overall height of the electronic package can be reduced and the heat dissipation efficiency of the electronic package can be improved also.

IPC Classes  ?

• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or

Abstract

An electronic package and a manufacturing method thereof are provided, in which a first optoelectronic element having a first optical fiber connection portion is disposed on an electronic module, a second optoelectronic element having a second optical fiber connection portion is disposed on a first level layer of a lower carrying portion of a step-shaped carrier structure, and the electronic module is disposed on a second level layer of the step-shaped carrier structure and the second optoelectronic element having the second optical fiber connection portion, so that the electronic module is electrically connected to the second optoelectronic element having the second optical fiber connection portion. Thereby, two optoelectronic elements having optical fiber connection portions can be easily and vertically integrated, and the second optoelectronic element can be stably carried by the step-shaped carrier structure.

IPC Classes  ?

• G02B 6/42 - Coupling light guides with opto-electronic elements

Abstract

An electronic package and a manufacturing method thereof are provided, in which a first barrier body and a second barrier body are disposed respectively, and a heat dissipation structure is formed with a hole thereon. Thereby, gas in the heat dissipation structure can be discharged via the hole, so as to prevent the gas from remaining in a thermal conductive layer and affecting the heat dissipation effect.

IPC Classes  ?

• H01L 23/04 - ContainersSeals characterised by the shape
• H01L 21/50 - Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups or
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/42 - Fillings or auxiliary members in containers selected or arranged to facilitate heating or cooling

Abstract

An electronic package and a manufacturing method thereof are provided, in which an electronic component is disposed on a substrate and covered with an encapsulation layer, and a frame body is embedded in the encapsulation layer and protrudes from the substrate. Therefore, the frame body can disperse thermal stress, thereby preventing warping from occurring to the electronic package.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/552 - Protection against radiation, e.g. light

Abstract

An electronic package and a manufacturing method thereof are provided, in which an electronic element stacking structure is disposed on a carrier structure to integrate multiple chips into a single package, so that the electronic package can meet with the requirements of miniaturization without increasing the layout area of the carrier structure.

IPC Classes  ?

• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices

Abstract

An electronic package is provided in which an electronic module and a heat dissipation structure combined with the electronic module are disposed on a carrier structure, and at least one adjustment structure is coupled with the heat dissipation structure and located around the electronic module. Therefore, the adjustment structure disperses thermal stress to avoid warpage of the electronic module.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/367 - Cooling facilitated by shape of device
• H01L 23/42 - Fillings or auxiliary members in containers selected or arranged to facilitate heating or cooling
• H01L 23/498 - Leads on insulating substrates
• H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for
• H05K 1/02 - Printed circuits Details

Abstract

An electronic package is provided and includes: a thermally conductive chip; a circuit structure having a circuit layer; and an electronic component disposed between the circuit structure and the thermally conductive chip and electrically connected to the circuit layer, so as to dissipate the heat generated during the operation of the electronic component via the thermally conductive chip. A method of manufacturing the electronic package is further provided.

IPC Classes  ?

• H01L 23/367 - Cooling facilitated by shape of device
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

An electronic package and a heat dissipation structure thereof are provided, in which a supporting member of the heat dissipation structure is disposed around an outer periphery of a central area and has grooves at corner areas. In this way, the grooves can avoid stress concentration in the corner areas, and the rest of the supporting member can well connect and fix the heat dissipation structure and a carrying structure, so as to suppress warpage of the entire electronic package and prevent delamination.

IPC Classes  ?

• H01L 23/367 - Cooling facilitated by shape of device
• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

An electronic package and a manufacturing method thereof are provided, in which an electronic module including a bridging component and an electronic component is partially arranged on a carrying structure and partially protrudes outside the carrying structure, and a photonic component is electrically connected to the protruding part of the electronic module. With this configuration, the layout area of the carrying structure can be reduced to meet the requirement of miniaturization.

IPC Classes  ?

• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
• H01L 23/28 - Encapsulation, e.g. encapsulating layers, coatings
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

An electronic package and a manufacturing method thereof are provided, in which an offset suppression layer is formed on a carrier, a first electronic element and a second electronic element are respectively disposed on the offset suppression layer, and an encapsulant is formed on the offset suppression layer to respectively cover the first electronic element and the second electronic element. The offset suppression layer effectively suppresses or prevents possible offset caused by the encapsulant to the first electronic element and the second electronic element, thereby avoiding yield loss of the semiconductor package.

IPC Classes  ?

• H01L 23/373 - Cooling facilitated by selection of materials for the device
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

An electronic package and a manufacturing method thereof are provided, in which a supporting structure having a supporting body is disposed on a carrying structure and is in contact with or in proximity to an electronic component, and a barrier structure is disposed on the supporting body, such that the electronic component is exposed from an opening of the barrier structure. Furthermore, a thermal conduction layer is formed on the electronic component exposed from the opening of the barrier structure, and the barrier structure blocks or surrounds the thermal conduction layer on the electronic component, thereby preventing the thermal conduction layer from overflowing.

IPC Classes  ?

• H01L 23/367 - Cooling facilitated by shape of device
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/373 - Cooling facilitated by selection of materials for the device

Abstract

A packaging structure is provided and includes: an electronic module; an encapsulation layer having a first surface and a second surface opposing the first surface and covering the electronic module; a protecting layer formed on the second surface of the encapsulation layer; and a heat conduction layer formed on the protecting layer. An electronic package including the packaging structure and methods for manufacturing the packaging structure and the electronic package are further provided.

IPC Classes  ?

• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

An electronic package and a heat dissipation structure thereof are provided, in which supporting members of the heat dissipation structure are arranged in edge areas, and no supporting member is arranged in corner areas. In this way, the supporting members are interrupted at the corner areas, so that stress can be prevented from concentrating in the corner areas, and the entire electronic package can be prevented from warping and delamination.

IPC Classes  ?

• H01L 23/367 - Cooling facilitated by shape of device
• H01L 23/00 - Details of semiconductor or other solid state devices