A data storage device includes one or more memory device and a controller that is DRAM-less coupled to the one or more memory devices. The controller is configured to receive a command from a host device, begin execution of the command, and receive an abort request command for the command. The command includes pointers that direct the data storage device to various locations on the data storage device where relevant content is located. Once the abort command is received, the content of the host pointers stored in the data storage device RAM are changed to point to the HMB. The data storage device then waits until any already started transactions over the interface bus that are associated with the command have been completed. Thereafter, a failure completion command is posted to the host device.
Embodiments of the present disclosure generally relate to housings for, e.g., memory devices and electronic devices, and to processes for forming such housings. In an embodiment, an article for housing at least a portion of an electronic device is provided. The article includes a first component comprising a thermoplastic and a biodegradable filler or polymer, and a second component disposed on at least a portion of the first component, the second component comprising a plurality of layers. The article has a scratch visibility load of about 200 gms or more, an electrostatic discharge static voltage of about 100 V or less, a thermal conductivity of about 0.28 W/mK or more, or combinations thereof.
G11B 33/14 - Reducing influence of physical parameters, e.g. temperature change, moisture, dust
B32B 15/085 - Layered products essentially comprising metal comprising metal as the main or only constituent of a layer, next to another layer of a specific substance of synthetic resin comprising polyolefins
A semiconductor structure includes a doped single crystalline semiconductor material layer, a metal or metal alloy source contact layer located over a back side of the doped single crystalline semiconductor material layer, a dielectric isolation layer located over a front side of the doped single crystalline semiconductor material layer, an alternating stack of insulating layers and electrically conductive layers located over the dielectric isolation layer, a memory opening vertically extending through the alternating stack and the dielectric isolation layer and at least partially through the doped single crystalline semiconductor material layer, a memory film and a vertical semiconductor channel located within the memory opening, such that the vertical semiconductor channel vertically extends through the dielectric isolation layer and into the doped single crystalline semiconductor material layer, and a single crystalline semiconductor pedestal contacting the doped single crystalline semiconductor material layer and the vertical semiconductor channel.
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
A Data Storage Device (DSD) receives weights for a plurality of layers of a neural network with layer information associating the weights with one or more layers. The received weights are stored in at least one Non-Volatile Memory (NVM) of the DSD using different storage characteristics based at least in part on the received layer information. The different storage characteristics include at least one of different storage locations, different storage techniques, and different storage maintenance settings. In another aspect, a first group of weights is requested by a host device for processing one or more first layers. The first group of weights is received by the host device and loaded into at least one memory of the host device. A second group of weights is requested from the DSD for processing one or more additional layers of the neural network before computations complete for the one or more first layers.
A thermal interface material for a semiconductor package includes three separate layers or portions—a first layer, a second layer and a metal layer. The metal layer is provided between the first layer and the second layer. The second layer defines a plurality of apertures and the metal layer defines a plurality of stubs. The first layer, the second layer and the metal layer are combined to form the thermal interface material. During formation, the plurality of stubs are at least partially received within respective apertures of the plurality of apertures defined by the second layer. When the thermal interface material is placed on an integrated circuit of the semiconductor package, the stubs contact the top surface of the integrated circuit to dissipate heat.
A data storage device includes an error correction code (ECC) system and a decoder gear determination system. The decoder gear determination system dynamically enhances error correction capabilities of a decoder of the ECC system should the decoder fail to decode a codeword. The decoder gear determination system enhances the error correction capabilities of the decoder prior to initiating a gear switch, in which another decoder, with higher error correction capabilities, is used to decode the codeword. The decoder gear determination system enhances the error correction capabilities of the decoder by deriving information about the failed decoding attempt. The derived information is used to generate an updated decoding parameter that is provided to the decoder. The decoder attempts a subsequent decoding process on the codeword using the updated decoding parameter.
A storage device minimizes updates to compressed msets based on a priority criterion. The storage device includes a memory including a logical-to-physical (L2P) table divided into msets that include a range of entries in the L2P table. The storage device also includes memory to cache a first set of msets. A controller on the storage device accesses the first set of msets to quickly read data from and write data to the memory device. The controller determines a uLayer state for a first mset in the first set of msets, a read ratio for the first mset, a prediction for the first mset, and/or a queue depth for the first mset in determining whether the first mset meets the priority criterion and is ready for compression. The controller assigns a high priority to the first mset if the first mset meets the priority criterion and compresses the first mset.
As block sizes in NAND memory continue to increase in size and density, in can be useful to access less than all of the block, such as sub-block or subset of the blocks NAND strings, in order to reduce read disturbs, reduce power consumption, and increase operating speeds. Although this sort of separation of sub-block can be achieved by independently biasable select gates, the sort of select gate structure can face processing difficulties, particularly at the source side of three dimensional NAND structures. To avoid these difficulties while still providing individually selectable sub-blocks, the following introduces word line based selectors, where multiple word lines of a blocks are programmed with different sets of threshold voltages, allowing them to be biased for individual access of sub-blocks. Alternatively, source side select gate electrical isolation is implemented using ion implantation on the source select gates to raise threshold voltages on different subsets.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
G11C 16/08 - Address circuitsDecodersWord-line control circuits
G11C 16/16 - Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
G11C 16/28 - Sensing or reading circuitsData output circuits using differential sensing or reference cells, e.g. dummy cells
G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H10D 64/66 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
H10D 80/30 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising integrated circuit processor chips
A data storage device includes a first partition, a second partition and a bandwidth allocation system. The bandwidth allocation system dynamically determines an amount of bandwidth that will be allocated to host operations and internal operations that are executed by the data storage device. The amount of bandwidth that is allocated is either fixed or is linearly varied according to the determined storage state of the data storage device. The determined storage state of the data storage device is based on an amount of available memory blocks in the first partition of the data storage device and an amount of available memory blocks in the second partition of the data storage device.
A data storage device includes a memory device, a random access memory (RAM) device, and a controller coupled to the memory device and the RAM device. The controller is configured to determine a workload type of the data storage device, determine to store at least a portion of a compressed logical to physical translation table (ZCAT) in the RAM device based on the workload type, and utilize a remaining portion of the RAM device to perform background operations. The controller is further configured to determine a persistence or temperature of the ZCAT, where the portion of the ZCAT stored to the RAM device is based on the persistence and/or the temperature of the ZCAT. The remaining portion of the ZCAT is stored in the HMB, where the remaining portion may update any out-of-date ZCAT entries.
A data storage device includes a write abort prediction system that monitors a number of write aborts that occur over a monitoring period. The write abort prediction system uses the monitored number of write aborts to predict or determine a probability regarding whether one or more write aborts will occur over another monitoring period. If the probability is over a write abort threshold, the write abort prediction system determines an operating state of the data storage device. Depending on the operating state of the data storage device and the determined probability, the write abort prediction system determines whether to alter the functionality of the data storage device. Altering the functionality of the data storage device reduces the risk that the data storage device will enter a read-only mode should one or more write aborts occur during execution of various commands.
G06F 3/00 - Input arrangements for transferring data to be processed into a form capable of being handled by the computerOutput arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
G06F 3/06 - Digital input from, or digital output to, record carriers
In the context of an electronic device such as a solid-state drive, implementation of a prying opening in a sidewall of an enclosure base, and positioned adjacent to a corresponding stepped structure along a sidewall of an enclosure cover, enables an effective prying mechanism enabling the disassembling of the electronic device. A stepped structure surface extending beyond the prying opening of the base forms a narrow pathway with the sidewall of the base, thus providing a structural mechanism to inhibit the transfer of ESD to the sensitive components of the device.
Embodiments disclosed herein are directed to a memory device, comprising a set of storage elements, a set of bitlines, where each bitline of the set of bitlines is associated with a respective storage element of the set of storage elements, and one or more control circuits. The one or more control circuits configured to during a memory operation performed on the set of storage elements: charge the set of bitlines to a high voltage level; in response to the set of bitlines reaching the high voltage level, float the set of bitlines; and discharge bitlines of the set of bitlines that are associated with selected storage elements of the set of storage elements.
A data storage device can use a jump range to identify whether a new write command received from a host is part of a sequential stream of write commands even though the logical block address of the new write command is not sequential to the logical block addresses of those other commands. However, using a fixed jump range can result in a new random write command being misclassified as a sequential write command, or vice versa. To address this problem, the embodiments presented herein describe a data storage device that uses a dynamic jump range based on a pattern of write commands previously received from the host. Other embodiments are provided.
A data storage device includes an unmap command analysis system that dynamically determines a size, or a LBA range, of an unmap command executed on the data storage device. The size of the unmap command is based, at least in part, on an amount of random data stored by the data storage device. The unmap command analysis system determines whether to check the amount of random data stored by the data storage device in response to a trigger event. When the trigger event is detected and the amount of random data is determined, the unmap command analysis system compares the amount of random data to information in an unmap command size table. The unmap command size table indicates which unmap command sizes are most efficient based on the determined amount of random data stored by the data storage device.
A data storage device can perform memory maintenance operations to maintain a healthy state of its memory. It is sometimes required to perform memory maintenance operations as foreground operations, but performing such operations in the foreground may exceed a time constraint established to guarantee a certain performance level. In one embodiment, the data storage device can throttle host commands to allow the memory maintenance operations to be performed in the foreground within the time constraint. Other embodiments are provided.
An alignment tool for a solder machine includes a base portion, a bracket and a solder wire alignment portion. Each portion is moveable with respect to the other portions. The base portion includes a laser alignment hole provided on a slope that extends from the base portion. The laser alignment hole is used to align the alignment tool to a laser of the solder machine. A solder wire feeder alignment slot of the solder wire alignment portion is used to align the bracket and the solder wire alignment portion with a solder wire feeder of the solder machine. When each portion of the alignment tool is in a desired position, fasteners of the alignment tool are tightened to secure each portion in the desired position. The alignment tool mirrors a correct alignment between the laser and the solder wire feeder and is usable for subsequent solder machine alignment processes.
A multi-layer printed circuit board (PCB) is fabricated using basalt fibers instead of glass fibers. Using basalt fibers in lieu of glass fibers makes the PCB more environmentally friendly without sacrificing mechanical and electrical properties. The multi-layer PCB includes a basalt fiber core comprised of a basalt fiber prepreg provided between two copper layers. A first copper layer and a second copper are coupled to different sides of the basalt fiber core. A first basalt fiber prepreg is coupled to the first copper layer and a second basalt fiber prepreg is coupled to the second copper layer.
As block sizes in NAND memory continue to increase in size and density, in can be useful to access less than all of the block, such as sub-block or subset of the blocks NAND strings, in order to reduce read disturbs, reduce power consumption, and increase operating speeds. Although this sort of separation of sub-block can be achieved by independently biasable select gates, the sort of select gate structure can face processing difficulties, particularly at the source side of three dimensional NAND structures. To avoid these difficulties while still providing individually selectable sub-blocks, the following introduces word line based selectors, where multiple word lines of a blocks are programmed with different sets of threshold voltages, allowing them to be biased for individual access of sub-blocks.
G11C 16/26 - Sensing or reading circuitsData output circuits
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
20.
Translation And Data Management In Storage Devices
With ever-increasing capacities and performance demanded in new storage devices, the number of control table data entries are increased to store more updates stemming from the increased number of read and/or write operations. To avoid becoming a bottleneck, devices, such as storage devices, and other similar methods and systems as described herein efficiently manage control table sets to reduce latency. This can be accomplished by designating a specific position for each control table set and storing updates to such control table sets in a designated position. Furthermore, data can be efficiently kept in the volatile memory, such as SRAM, or evicted from the volatile memory to the non-volatile memory, such as NAND. Determinations can occur for when the read/write operations should be performed using volatile memory or non-volatile memory. These determinations can be decided dynamically and based on the storage device state and incoming workload, resulting in lower overall latencies.
The present disclosure generally relates to split, non-operational power states for a data storage device. The data storage device can transition between the split, non-operational power states without advertising the transition to the host device. The power state parameters that are advertised to the host device are adjusted such that the host device is guided to the correct power decision based on the advertised power and duration. By splitting the non-operational power states, the data storage device does not incur additional transitional energy costs for short idle durations.
A controller maintains logical block address (LBA) to physical block address (PBA) mappings as mSets in a storage address table (SAT). Because the SAT may include many mappings, and, consequently, have a large size, the SAT may be stored in a distanced memory from the controller, such as a non-volatile memory device of the data storage device or a host memory buffer of a host device that is coupled to the data storage device. In order to optimize performance, a portion of the SAT may be stored as a compressed address table (CAT) in an internal memory of the controller or another volatile memory of the data storage device. During operation, the controller maintains an active range of mSets in the CAT by adding mSets to the CAT based on whether the LBA is sequential to the active range and a hit count of the active range.
A three-dimensional memory device includes alternating stacks of insulating layers and electrically conductive layers, where each of the alternating stacks laterally extends along a first horizontal direction, and the alternating stacks are laterally spaced apart from each other along a second horizontal direction by lateral isolation trenches, arrays of memory openings, where each array of memory openings vertically extends through a respective one of the alternating stacks, arrays of memory opening fill structures located within the arrays of memory openings, where each of the memory opening fill structures includes a respective vertical stack of memory elements and a vertical semiconductor channel, and composite lateral isolation trench fill structures located between a respective neighboring pair of the alternating stacks. Each of the composite lateral isolation trench fill structures includes a laterally alternating sequence of dielectric pillar structures and isolation opening fill structures arranged along the first horizontal direction.
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
Adding a bypass module and a pattern detector module to a data path of a controller will increase the efficiency of both sanitize block erase audit and sanitize crypto erase audit operations. The sanitize crypto erase audit skips an end to end (E2E) protection module to provide decrypted data to a static random access memory (SRAM) buffer and ultimately a host device through a direct memory access (DMA) module. The sanitize block erase audit utilizes the pattern detector module to provide a known pattern to the SRAM buffer and host through the DMA module. The bypass module and pattern detector module feed into a multiplexer (Mux) prior to the SRAM buffer.
A memory device includes a first-tier structure including a first first-tier alternating stack and a second first-tier alternating stack, a second-tier structure overlying or underlying the first-tier structure and including a first second-tier alternating stack and a second second-tier alternating stack that are laterally spaced apart from each other by a jumper alternating stack, and memory stack structures vertically extending through a respective set of at least two alternating stacks. Each of alternating stack includes a respective vertically alternating sequence of insulating layers and electrically conductive layers. An electrically conductive path electrically connects a first first-tier electrically conductive layer within the first first-tier alternating stack, a second first-tier electrically conductive layer within the second first-tier alternating stack, a first second-tier electrically conductive layer within the jumper alternating stack, a first layer contact via structure, and a second layer contact via structure.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
26.
Data Storage Device That Detects and Releases Bottlenecks in Hardware
A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a read command to read data from the memory device or a write command to write data to the memory device from a host device, determine whether a bottleneck exists in a data/control path between the host device and the memory device, wherein the bottleneck exists in a hardware module of the plurality of hardware modules, and execute a bottleneck release operation when the bottleneck exists in the data/control path between the host device and the memory device, wherein the bottleneck release operation is dependent on whether the bottleneck exists in the input queue. The bottleneck release operation includes changing a clock of the hardware module, moving the command to a different hardware module configured to process the command, and combinations thereof.
An apparatus includes a semiconductor wafer including a first die and a second die, each including, a selector circuit including a first input terminal coupled to a first die bond pad, a second input terminal, and an output terminal, the selector circuit configured to selectively couple the first input terminal and the second input terminal to the output terminal, a conductor selectively configured to couple the second input terminal to either a first power supply or a second power supply, and an address determined based on a signal value at the output terminal of the selector circuit.
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
28.
ADAPTIVE ERASE PULSE TO IMPROVE MEMORY CELL ENDURANCE AND ERASE TIME IN NON-VOLATILE MEMORY
To improve memory cell endurance and erase times for non-volatile memories, such as NAND memory, a sub-block based adaptive erase pulse is used. In a memory structure where the array is composed of blocks that have multiple sub-blocks, after applying an erase pulse to an erase selected block, one of the sub-blocks is erased verified and, if it fails to verify, the next erase pulse's duration is tuned based on the number of memory cells of that sub-block that fail to verify. If the first verified one of the sub-blocks verifies, the other sub-blocks of the erase selected block are erased verified, with the next erase pulse's duration tuned based on the number of the other sub-blocks that fail to verify.
G11C 16/16 - Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
29.
MEMORY DEVICE INCLUDING A GERMANIUM-CONTAINING SOURCE STRUCTURE AND METHODS FOR FORMING THE SAME
A memory device includes a semiconductor source line layer containing silicon and electrical dopants, an alternating stack of insulating layers and electrically conductive layers located over the semiconductor source line layer, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening. The memory opening fill structure includes a memory film, a vertical semiconductor channel including silicon that is laterally surrounded by the memory film, and a silicon-germanium structure contacting an end portion of the vertical semiconductor channel and contacting the semiconductor source line.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
30.
THREE-DIMENSIONAL MEMORY DEVICE WITH THROUGH-STACK CONTACT VIA STRUCTURES AND METHOD OF MAKING THE SAME
A memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through each layer within the alternating stack, a memory opening fill structure located in the memory opening and including a vertical stack of memory elements a vertical semiconductor channel, and a contact via structure. The contact via structure includes a conductive pillar portion vertically extending at least from a first horizontal plane including a bottommost surface of the alternating stack to a second horizontal plane including a topmost surface of the alternating stack, and an annular conductive fin portion laterally protruding from the conductive pillar portion and contacting one of the electrically conductive layers. A vertical stack of annular insulating plates laterally surrounds the conductive pillar portion and underlies the conductive fin portion.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
31.
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING SILICON OXYCARBIDE LINERS AND METHODS OF FORMING THE SAME
A memory device includes an alternating stack comprising silicon oxycarbide layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and containing a vertical semiconductor channel and a memory film including a ferroelectric material layer in direct contact with sidewalls the electrically conductive layers.
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H10B 51/10 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the top-view layout
H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
A data storage device includes a memory device and a controller coupled to the memory device. The controller includes a decoder multiplexer (mux) module, a plurality of request/response channels coupled to the decoder mux module, an arithmetic pipeline module coupled to the plurality of request/response channels, an arbiter module coupled to the plurality of request/response channels and the arithmetic pipeline module, a mux/arbiter module coupled to the arithmetic pipeline module, a random access memory (RAM) access module coupled to the decoder mux module and the mux/arbiter module, and a RAM coupled to the mux/arbiter module. The controller is configured to determine a pipeline depth value and a calculation parallelism value of the arithmetic pipeline module and configure the arithmetic pipeline module based on the determining.
The present disclosure generally relates to ensuring a data storage device consumes as little power as possible. Different HW modules in the data storage device can operate at different frequencies to ensure any bottleneck HW modules operate at as fast a frequency as possible, while non-bottleneck HW modules operate at slower frequencies and hence, consume less power. The frequency for each HW modules is dynamic and is adjusted based upon detected bottlenecks so that the data storage device can operate as efficiently as possible and consume as little power as possible.
A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening and including a memory film, a vertical semiconductor channel, and a semiconductor source cap structure which is at least partially laterally surrounded by the memory film and which contacts the vertical semiconductor channel, and a source layer contacting at least a first end surface segment of the semiconductor source cap structure.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
35.
CONTROL GATE SIGNAL FOR DATA RETENTION IN NONVOLATILE MEMORY
The nonvolatile memory includes a plurality of nonvolatile memory cells configured to store multiple data states; a word line connected to a control gate of at least one of the plurality of non-volatile memory cells; a control gate line to supply a control gate signal; a word line switch connected between the word line and the control gate line to control the potential applied to the word line from the control gate line; and a memory controller circuit. The memory controller circuit is configured to control a word line potential on the word line and a control gate potential on the control gate line and to control a state of the control gate. The memory controller circuit, when the nonvolatile memory transitions to a not-on state, is further configured to turn off the word line switch and to charge the control gate line to a charged potential.
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
36.
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING MULTI-LEVEL BRIDGE SUPPORT STRUCTURES AND METHODS FOR FORMING THE SAME
A semiconductor structure includes alternating stacks of insulating layers and electrically conductive layers which are located over a substrate and are laterally spaced apart among one another by first backside trenches and second backside trenches that are interlaced along a horizontal direction, first backside trench fill structures located in the first backside trenches, and second backside trench fill structures located in the second backside trenches. Each of the first backside trench fill structures includes a respective set of first backside bridge support structures comprising a first material, and each of the second backside trench fill structures includes a respective set of second backside bridge support structures comprising a second material that is different from the first material.
H01L 23/528 - Layout of the interconnection structure
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
37.
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING ETCH STOP METAL PLATES FOR BACKSIDE VIA STRUCTURES AND METHODS FOR FORMING THE SAME
A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers that is located on a front side of a source layer, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, a dielectric material portion laterally offset from the alternating stack, a connection via structure vertically extending through the dielectric material portion and contacting a front side surface of a metallic plate, and a backside contact pad in electrical contact with the metallic plate.
H01L 23/528 - Layout of the interconnection structure
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
38.
THREE-DIMENSIONAL MEMORY DEVICE INCLUDING COAXIAL DOUBLE CONTACT VIA STRUCTURES AND METHODS FOR FORMING THE SAME
A device structure includes an alternating stack of insulating layers and electrically conductive layers, a stepped dielectric material portion overlying and laterally contacting the alternating stack in the staircase region, and memory opening fill structures extending through the alternating stack. The electrically conductive layers include first electrically conductive layers and second electrically conductive layers overlying the first electrically conductive layers. Coaxial double contact via structures vertically extend through the stepped dielectric material portion. Each of the coaxial double contact via structures includes a respective inner layer contact via structure contacting a respective one of the first electrically conductive layers, and a respective outer layer contact via structure that laterally surrounds the respective inner layer contact via structure and contacts a respective one of the second electrically conductive layers.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
The present disclosure generally relates to an embedded physical layer (EPHY) for a field programmable gate array (FPGA). The EPHY for the FPGA is for a testing device that can receive and transmit in both the high speed PHYs, as well as low speed PHYs, such as MIPI PHYS (MPHYs), to meet universal flash storage (UFS) specifications. The testing device with the EPHY for the FPGA provides flexibility to support any specification updates without the need of application specific (ASIC) production cycles.
G01R 31/3183 - Generation of test inputs, e.g. test vectors, patterns or sequences
G01R 31/00 - Arrangements for testing electric propertiesArrangements for locating electric faultsArrangements for electrical testing characterised by what is being tested not provided for elsewhere
G06F 1/04 - Generating or distributing clock signals or signals derived directly therefrom
G06F 7/64 - Digital differential analysers, i.e. computing devices for differentiation, integration or solving differential or integral equations, using pulses representing incrementsOther incremental computing devices for solving difference equations
G06F 30/347 - Physical level, e.g. placement or routing
A data storage device including, in one implementation, a number of memory die packages disposed on a substrate within the data storage device. Each memory die package has a die density that includes one or more memory dies. The die density of each memory die package is configured to provide an even thermal distribution across the number of memory die packages. The respective die densities of two memory of the die packages are different from each other.
G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
G06F 119/02 - Reliability analysis or reliability optimisationFailure analysis, e.g. worst case scenario performance, failure mode and effects analysis [FMEA]
G06F 119/06 - Power analysis or power optimisation
G06F 119/08 - Thermal analysis or thermal optimisation
H01L 23/367 - Cooling facilitated by shape of device
The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller and a media unit. The capacity of the media unit is divided into a plurality of zones. The controller is configured to make informed use of errors by update zone metadata to indicate one or more first logical block addresses were skipped and to indicate the next valid logical block address is available to store data. The controller is further configured to update zone metadata to recommend to the host device to reset one or more full zones, to recommend to the host device to transition one or more open zones to a full state, to alert the host device that one or more open zones have been transitioned to the full state, and to notify the host device of the writeable zone capacity of each of the plurality of zones.
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 11/20 - Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller comprising first random access memory (RAM1), second random access memory (RAM2), and a storage unit divided into a plurality of streams. When a write command is received to write data to a stream, change log data is generated and stored in the RAM1, the previous delta data for the stream is copied from the RAM2 to the RAM1 to be updated with the change log data, and the updated delta data is copied to the RAM2. The delta data stored in the RAM2 is copied to the storage unit periodically. The controller tracks which delta data has been copied to the RAM2 and to the storage unit. During a power failure, the delta data and the change log data are copied from the RAM1 or the RAM2 to the storage unit.
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 1/30 - Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
G06F 12/0804 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
A memory device includes a first-tier alternating stack of first insulating layers and first electrically conductive layers, a source layer overlying the first-tier alternating stack, a second-tier alternating stack of second insulating layers and second electrically conductive layers overlying the source layer, a memory opening vertically extending through the first-tier alternating stack, the source layer, and the second-tier alternating stack, a memory opening fill structure located in the memory opening and comprising a vertical stack of first memory elements and a vertical semiconductor channel vertically extending through each of the first electrically conductive layers, the source layer, and the second electrically conductive layers, and having a sidewall in contact with the source layer, and a bottom drain region in contact with a bottom portion of the vertical semiconductor channel.
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/30 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
44.
MINI-PUMP LEVEL SHIFTER FOR ROBUST SWITCHING OPERATION UNDER LOW VDD ENVIRONMENT
On memory die and other circuits, some parts may operate at a VDD logic level while other elements operate at a higher logic level, such as at or near the die's supply level VSUP. To reduce power consumption and increase operating speeds, VDD levels are moving to increasingly lower voltages. To raise the logic signal from the lower level to the higher, level shifters can be used. However, as the gap between the supply level VSUP and VDD widens, it can become difficult for a level shifter to reliably raise a logic signal operating at the VDD level to the VSUP level. The address this problem, the following introduces a small charge pump to boost the input logic signals for level shifter circuits to allow them to reliably generate an output logic signal at the VSUP level from an input logic signal at low VDD levels.
A data storage device and method for device-initiated hibernation are provided. In one embodiment, the data storage device comprises a non-volatile memory and a controller. The controller is configured to: receive, from a host during a set-up phase of a hibernation process, a plurality of write commands with a current state of a volatile memory in the host; store the plurality of write commands in a queue, wherein the plurality of write commands are not executed during the set-up phase of the hibernation process; receive a trigger from the host to perform an execution phase of the hibernation process; and in response to receiving the trigger, execute the plurality of write commands to store the current state of the host's volatile memory in the non-volatile memory of the data storage device. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.
To reduce spikes in the current used during read operations by a system of multiple NAND memory dies operated in parallel, relative delays between the memory dies are introduced before high current sub-operations of the read. The occurrence of the primary current peak in the read operation can depend upon the extent to which a selected memory block is programmed. For example, in a closed block the primary peak occurs when ramping up unselected word lines, while for an open block the primary read peak occurs when the bit lines are charged up. To account for these differences, determining where to introduce relative delays is based on the extent to which a block is programmed. For example, if a block fully or largely closed, delays are introduced before ramping up the unselected word lines, but otherwise adding the delays before charging up bit lines.
To improve programming performance in NAND memory, while maintaining programming accuracy and reducing program disturb, the channel pre-charge phase before a programming pulse can be eliminated. Instead, a read recovery phase after the program verify directly discharges a selected word line from the verify voltage to a negative word line voltage, with non-selected word lines being directly discharged from the read bypass voltage to the negative word line voltage. From the negative word line voltage, the word lines are then ramped up to ground and then on the bias levels of the following programming pulse. These conditions can drive electrons from the charge storage region of the selected memory cell, resulting in a high degree of channel boosting and much less program disturb. Variations of the technique can be applied to NAND memory operable in a sub-block mode where it can be difficult to use the typical channel pre-charge.
A memory package includes a plurality of memory dies, each of which has a plurality of memory blocks with arrays of memory cells. The memory dies include user data dies that contain user data and an XOR die that contains XOR data. The memory package also includes circuitry for reading the user data and the XOR data. The circuitry is configured to detect a read error during a read operation in a failed die of the plurality of user data dies and read some of the user data of the user data dies besides the failed die and reading some of the XOR data of the XOR die. The circuitry is also configured to perform a read recovery operation that includes an XOR operation using, as inputs, the user data of the user data dies besides the failed die and the XOR data of the XOR die.
Embodiments of the present technology provide memory cards intelligently designed to provide protection when mistakenly inserted into non-memory card hosts. Embodiments achieve such protection with less footprint/circuitry than existing fail-safe solutions, and without electrical overstress-causing offset voltages characteristic of existing fail-safe solutions. To realize these advantages, a memory card of the present technology includes a fail-safe reference voltage supply circuit that operates in a “fail-safe mode” by default, and exits and re-enters the fail-safe mode in response to voltage mode driver output enable (OE) signals.
A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack and a memory opening fill structure located in the memory opening. A Group IV-containing material portion is formed by selective deposition on an end portion of the vertical semiconductor channel. Alternatively, a backside semiconductor cap structure can be formed directly on a bottom surface of the vertical semiconductor channel by selective or non-selective deposition of a semiconductor material.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
51.
THREE-DIMENSIONAL MEMORY DEVICES HAVING CHANNEL CAP STRUCTURES AND METHODS FOR FORMING THE SAME
A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack and a memory opening fill structure located in the memory opening. A Group IV-containing material portion is formed by selective deposition on an end portion of the vertical semiconductor channel. Alternatively, a backside semiconductor cap structure can be formed directly on a bottom surface of the vertical semiconductor channel by selective or non-selective deposition of a semiconductor material.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
52.
THREE-DIMENSIONAL MEMORY DEVICE INCLUDING SCHOTTKY BARRIER SOURCE CONTACTS AND METHODS OF FORMING THE SAME
A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located over a source layer; a memory opening vertically extending through the alternating stack; and a memory opening fill structure located in the memory opening and including a memory film, a vertical semiconductor channel laterally surrounded by the memory film and in contact with the source layer, a dielectric metal oxide liner laterally surrounded by the vertical semiconductor channel, and a dielectric core laterally surrounded by the dielectric metal oxide liner.
H01L 23/528 - Layout of the interconnection structure
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
A solid state drive (SSD) wafer device includes first and second semiconductor wafers coupled together. The first wafer may include a number of memory dies with die bond pads, and the second wafer may include a number of electrical interconnects, each including first and second terminals at opposed ends of the electrical interconnect. When the wafers are bonded together, the first terminals of the second wafer are bonded to the die bond pads of the memory dies of the first wafer. The second terminals are left exposed to couple with an SSD controller, which controls the transfer of data and signals between the memory dies of the first wafer and a host device such as a server in a datacenter.
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
54.
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING MEMORY OPENINGS ARRANGED IN NON-EQUILATERAL TRIANGULAR LAYOUT AND METHOD OF MAKING THEREOF
A memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, where a smallest unit shape of three nearest neighbor memory openings is a non-equilateral triangle, and memory opening fill structures located in the memory openings, where each of the memory opening fill structures includes a vertical semiconductor channel and a vertical stack of memory elements.
H01L 23/528 - Layout of the interconnection structure
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
55.
THREE-DIMENSIONAL MEMORY DEVICE INCLUDING A SOURCE STRUCTURE SURROUNDED BY INNER SIDEWALLS OF VERTICAL SEMICONDUCTOR CHANNELS AND METHODS OF FORMING THE SAME
A three-dimensional memory device includes a source structure having a portion surrounded by inner sidewalls of cylindrical vertical semiconductor channels.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
56.
NOISE REDUCTION IN SENSE AMPLIFIERS FOR NON-VOLATILE MEMORY
Techniques are presented to reduce sense amplifier noise from parasitic capacitances that can affect the internal transfer of a data value from a data latch to a sensing node. To transfer the data value, the sensing node is pre-charged and the data value used to set the control gate voltage on a transistor in a discharge path for the sensing node. In the discharge path, the transistor is connected in series with a switch, so that when the switch is turned on, the data value on the transistor's control gate will determine whether or not the sensing node discharges. To reduce noise in the process, before the data value is used to bias the discharge path transistor's control gate, a node between the transistor and switch is charged. Additionally, a lower voltage level can be used to turn on the discharge path switch.
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
57.
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING COMPOSITE DIELECTRIC ISOLATION STRUCTURE IN A STAIRCASE REGION AND METHODS OF FORMING THE SAME
A three-dimensional memory device includes laterally spaced apart vertical stacks of electrically conductive layers and insulating layers. A composite dielectric isolation structure provides electrical isolation between neighboring pairs of vertical stacks. The composite dielectric isolation structure includes at least one retro-stepped dielectric material portion, and may further include at least one finned insulating support structure or a vertical stack of dielectric material plates.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
58.
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING COMPOSITE DIELECTRIC ISOLATION STRUCTURE IN A STAIRCASE REGION AND METHODS OF FORMING THE SAME
A three-dimensional memory device includes laterally spaced apart vertical stacks of electrically conductive layers and insulating layers. A composite dielectric isolation structure provides electrical isolation between neighboring pairs of vertical stacks. The composite dielectric isolation structure includes at least one retro-stepped dielectric material portion, and may further include at least one finned insulating support structure or a vertical stack of dielectric material plates.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
59.
THREE-DIMENSIONAL MEMORY DEVICE INCLUDING A SOURCE STRUCTURE SURROUNDED BY INNER SIDEWALLS OF VERTICAL SEMICONDUCTOR CHANNELS AND METHODS OF FORMING THE SAME
A three-dimensional memory device includes a source structure having a portion surrounded by inner sidewalls of cylindrical vertical semiconductor channels.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
The present disclosure generally relates to reducing link-up time between an upstream device and a downstream device. Rather than re-coordinating the link between devices each time, knowledge gained from a previous link-up is used to speed up the link-up. Typically, when both the upstream device and the downstream device have not changed, then the coefficient values for downstream port (DSP) transmission (Tx) equilibrium (EQ) that resulted in a desired bit error rate (BER) should not have changed either. Hence, rather than exchanging coefficients, the previous values can be reused with confidence eliminating the need to exchange coefficients. In so doing, the link-up process is much faster and system resources are not wasted on unnecessary coefficient exchanges.
Non-volatile memory cells are programmed by raising a voltage applied to a selected word line to a program voltage during a first time period of a programming process for selected non-volatile memory cells connected to the selected word line; programming the selected non-volatile memory cells using the program voltage during a second time period after the first time period; testing, during the first time period, whether the voltage applied to the selected word line is greater than one or more intermediate voltages; and elongating the first time period during the first time period if the voltage applied to the selected word line is not greater than one or more of the intermediate voltages.
In NAND memory, data sanitization allows a relatively small unit of data (e.g., less than a block) to be effectively destroyed by increasing threshold voltages of memory cells from their programmed threshold voltage to the highest threshold state. To reduce the amount of disturb on memory cells not selected for data sanitization, prior to applying a program voltage to a target word line, a hole based pre-charge operation is performed. More specifically, for NAND strings having a memory cell selected for data sanitation, prior to applying a programming pulse to the corresponding word line, a soft erase operation is performed. After biasing the memory cells and select gates of the NAND strings to a low voltage, a soft erase voltage pulse is applied to the source lines and bit line to pre-charge the NAND string channels with holes.
An apparatus is provided that includes a memory cell having a reversible resistance-switching memory element coupled in series with a selector element. The selector element has a first resistance. The resistance-switching memory element is configured to reversibly switch between a second resistance and a third resistance. The memory cell may be selectively configured as either a re-writeable memory cell or a one-time programmable memory cell. The memory cell functions as a one-time programmable memory cell regardless of whether the resistance-switching memory element has the second resistance, the third resistance, or is electrically shorted.
G11C 17/16 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
G11C 17/18 - Auxiliary circuits, e.g. for writing into memory
H10B 20/25 - One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
A memory system performs an erase process for the non-volatile memory cells including performing erase verify for the non-volatile memory cells. The erase verify comprises comparing threshold voltages of the non-volatile memory cells to an erase verify reference voltage and determining whether an amount of the non-volatile memory cells having a threshold voltage greater than the erase verify reference voltage is less than an allowed bit count. During the erase process, the system compares threshold voltages of the non-volatile memory cells to an intermediate reference voltage that is greater than the erase verify reference voltage and determines an amount of non-volatile memory cells having threshold voltages greater than the intermediate reference voltage. The Allowed Bit Count is increased (during the erase process) by the amount of non-volatile memory cells having threshold voltages greater than the intermediate reference voltage.
A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, where the electrically conductive layers have different lateral extents that decrease along an upward vertical direction from a bottommost insulating layer to a topmost insulating layer of the insulating layers, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening and including a vertical stack of memory elements and a vertical semiconductor channel, and a layer contact via structure vertically extending through a subset of the electrically conductive layers and a subset of the insulating layers that includes the bottommost insulating layer, contacting a top surface of a topmost electrically conductive layer within the subset of the electrically conductive layers, and having a topmost surface below a horizontal plane including a topmost surface of the alternating stack.
H01L 23/528 - Layout of the interconnection structure
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
66.
THREE-DIMENSIONAL MEMORY DEVICE WITH BACKSIDE WORD LINE CONTACT VIA STRUCTURES AND METHODS OF FORMING THE SAME
A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening and including a vertical stack of memory elements and a vertical semiconductor channel, and a layer contact via structure vertically extending through a subset of the electrically conductive layers and a subset of the insulating layers that includes the bottommost insulating layer, and contacting a surface of a topmost electrically conductive layer within the subset of the electrically conductive layers.
H01L 23/528 - Layout of the interconnection structure
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
Noise injection procedures implemented on the die of a non-volatile memory (NVM) array are disclosed. In one example, noise is injected into data by adjusting read voltages to induce bit flips while using feedback to achieve a target amount of information degradation. In another example, random data is iteratively combined with itself to achieve a target percentage of random 1s or 0s, then the random data is combined with data read from the NVM array. In other examples, pixels are randomly zeroed out to emulate dead charge coupled device (CCD) pixels. In still other examples, the timing, voltage, and/or current values used within circuits while transferring data to/from latches or bitlines are adjusted outside their specified margins to induce bit flips to inject noise into the data. The noise-injected data may be used, for example, for dataset augmentation or for the testing of deep neural networks (DNNs).
A three-dimensional memory device includes alternating stacks of insulating layers and electrically conductive layers. The alternating stacks are laterally spaced apart among one another by backside isolation assemblies. At least one of the backside isolation assemblies generally extends along a first horizontal direction with lateral undulations along a second horizontal direction that is perpendicular to the first horizontal direction. At least one of the alternating stacks has a modulation in width along the second horizontal direction as a function of a position along the first horizontal direction. Memory stack structures vertically extend through a respective one of the alternating stacks. Each of the backside isolation assemblies includes a respective laterally alternating sequence of backside dielectric isolation walls and backside dielectric support pillar structures.
H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/50 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
A data storage device includes a memory device and a controller. The controller is configured to select a source block, read metadata associated with the source block and compare to a logical block address to physical block address (L2P) table, determine if a flash management unit (FMU) of the source block is valid, and add a new entry associated with the FMU into a valid FMU buffer when the FMU of the source block is determined to be valid. The controller is further configured to determine that the source block has been fully validated and select a next source block based on a valid counter. The valid counter corresponds to an amount of valid data of the next source block.
A method of forming a memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming memory openings through the alternating stack, forming memory opening fill structures in the memory openings including respective vertical stack of memory elements and a respective vertical semiconductor channel, forming a lateral isolation trench through the alternating stack, forming lateral recesses by removing the sacrificial material layers selective to the insulating layers and the memory opening fill structures, depositing a first tungsten layer in the lateral recesses using a first tungsten deposition process in which a fluorine-containing tungsten precursor gas is used as a reactant, and depositing a second tungsten layer on the first tungsten layer in the lateral recesses using a second tungsten deposition process in which a fluorine-free tungsten precursor gas is used as a reactant.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
71.
TRANSCEIVER ARCHITECTURE WITH LOW KICK-BACK NOISE AND PAD CAP
Embodiments of the present technology provide transceivers intelligently designed to reduce voltage kickback and I/O pad capacitance. A transceiver of the present technology can reduce voltage kickback by dynamically tracking I/O pad voltage at gate terminals of reference voltage signal-receiving MOS devices of a voltage mode cascoded driver implemented in the transceiver. By tracking I/O pad voltage, embodiments can reduce/avoid rapidly changing voltage differentials across the reference voltage signal-receiving MOS devices-thereby reducing voltage kickback. By reducing voltage kickback, embodiments can maintain reliability and improve performance for the transceiver. Tracking I/O pad voltage at the gate terminals of the reference voltage signal-receiving MOS devices can also reduce I/O pad capacitance of the transceiver-thereby improving performance for the transceiver.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
A device structure includes an alternating stack of insulating layers and electrically conductive layers, a dielectric material portion overlying the alternating stack, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, and a coaxial double contact via structure. The coaxial double contact via structure includes an inner layer contact via structure contacting the first-type electrically conductive layer; at least one insulating spacer layer that laterally surrounds the inner layer contact via structure; and an outer layer contact via structure including a tubular conductive portion that laterally surrounds the at least one insulating spacer layer and contacting the second-type electrically conductive layer.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
73.
ACTIVE CURRENT CONSUMPTION SAVE MODE FOR NON-VOLATILE MEMORY USING FAST PROGRAMMING
A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and disposed in memory holes coupled to bit lines. A control means successively applies each of a series of pulses of a program voltage to selected ones of the word lines while simultaneously applying one of a bit line program voltage and a bit line inhibit voltage to ones of the bit lines coupled to the memory holes containing groups of the memory cells connected to the selected ones of the plurality of word lines to program the groups of the memory cells with data. The control means maintains a voltage applied to ones of the plurality of bit lines as the bit line inhibit voltage in response to the ones of the plurality of bit lines remaining unselected when programming a next one of the groups of the memory cells.
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
G11C 8/08 - Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
74.
METHOD OF MAKING HIGH ASPECT RATIO OPENINGS USING MULTIPLE CLADDING MASKS AND APPARATUS FOR IMPLEMENTING THE SAME
A method includes forming an alternating stack of first material layers and second material layers over a substrate, forming an etch mask material layer over the alternating stack, loading the etch mask material layer, the alternating stack, and the substrate into an integrated processing apparatus including a plurality of etch chambers and at least one cladding liner deposition chamber; and iteratively performing multiple instances of a unit processing sequence without breaking vacuum. The unit processing sequence includes a respective cladding liner deposition process in which a respective cladding material is anisotropically deposited over the etch mask material layer in a respective one of the at least one cladding liner deposition chamber, and a respective anisotropic etch process in which respective portions of the alternating stack that are not masked by the etch mask material layer are anisotropically etched in a respective etch chamber selected from the plurality of etch chambers.
H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
75.
THREE-DIMENSIONAL MEMORY DEVICE WITH BACKSIDE SUPPORT PILLAR STRUCTURES AND METHODS OF FORMING THE SAME
A three-dimensional memory device includes alternating stacks of insulating layers and electrically conductive layers. The alternating stacks are laterally spaced apart among one another by backside isolation assemblies. At least one of the backside isolation assemblies generally extends along a first horizontal direction with lateral undulations along a second horizontal direction that is perpendicular to the first horizontal direction. At least one of the alternating stacks has a modulation in width along the second horizontal direction as a function of a position along the first horizontal direction. Memory stack structures vertically extend through a respective one of the alternating stacks. Each of the backside isolation assemblies includes a respective laterally alternating sequence of backside dielectric isolation walls and backside dielectric support pillar structures.
H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/50 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
76.
NON-VOLATILE MEMORY WITH FASTER POST-ERASE DEFECT TESTING
As part of the erase operation for a memory block, one or more post-erase tests can be incorporated into the erase operation to see whether the block has grown any defects. After erasing a block and verifying the erase, the post-erase tests can be performed on the block. As these test involve biasing the block and performing a sensing operation, these post erase tests come with a time penalty. To reduce the associated time penalty and improve memory performance while incorporating the defect tests into the erase process, when biasing the memory array for the post-erase defect tests different ramp rates can be used. In particular, faster ramp rates for bias levels, such those applied to the word lines of the block, are used for the post-erase tests than are used for the same bias level when performing the standard read, program verify, or read verify operations.
G11C 29/44 - Indication or identification of errors, e.g. for repair
G06F 12/1009 - Address translation using page tables, e.g. page table structures
G11C 29/12 - Built-in arrangements for testing, e.g. built-in self testing [BIST]
77.
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING INSULATED GATE LOCATED OVER A TOP SOURCE LAYER FOR APPLYING GIDL ERASE VOLTAGE AND METHOD FOR MANUFACTURING THE SAME
A memory device includes a source layer, an alternating stack of insulating layers and electrically conductive layers located over a proximal horizontal surface of the source layer, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening and containing a memory film and a vertical semiconductor channel, a source-control-gate dielectric located over a distal horizontal surface of the source layer which is opposite to the proximal surface of the source layer, and a source-control electrode located over the source-control-gate dielectric.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
78.
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING MULTI-LEVEL WORD LINE CONTACT WELLS AND METHODS FOR MANUFACTURING THE SAME
A memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings and including a respective memory film and a respective vertical semiconductor channel, contact wells vertically extending through a respective subset of layers of the alternating stack that includes a topmost insulating layer of the insulating layers, dielectric fill structures located in the contact wells, and an array of contact via structures vertically extending through the respective dielectric fill structure in each of the contact wells and contacting a top surface of a respective electrically conductive layer within a subset of the electrically conductive layers, the subset of the electrically conductive layers including a plurality of electrically conductive layers that are vertically spaced apart.
H01L 23/528 - Layout of the interconnection structure
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
Technology is disclosed herein for a storage system that reduces the Icc during open block reads. A lower than nominal voltage may be applied to the bit lines during open block reads, which reduces Icc. A nominal bit line voltage may be used during closed block reads. The lower than nominal bit line voltage may be combined with using a lower than nominal read pass voltage (Vread) to unprogrammed word lines during the open block read. The lower than nominal Vread has a lower magnitude than a nominal Vread used during a closed block read. Combining the lower than nominal bit line voltage with the lower than nominal Vread to unprogrammed word lines further reduces Icc during open block reads. The ramp rate of Vread may be relaxed (made slower) during at least some open block reads in combination with the lower than nominal bit line voltage.
A memory device includes at least one alternating stack of insulating layers and electrically conductive layers overlying a source layer, a memory opening vertically extending through the at least one alternating stack, and a memory opening fill structure located in the memory opening and containing a vertical stack of memory elements and a vertical semiconductor channel. The memory opening fill structure includes a lateral protrusion having a tapered sidewall surface such that a lateral extent of the lateral protrusion decreases with a vertical distance from the source layer. One of the electrically conductive layers of the at least one alternating stack is a taper-containing electrically conductive layer that is located at a level of the lateral protrusion of the memory opening fill structure.
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
A storage device is disclosed. The storage device is configured to: determine data states for a first set of memory cells of a first neighboring word line of the and a second set of memory cells of a second neighboring word line, the first and the second neighboring word lines being adjacent to a selected word line; identify a zone of a plurality of zones for each data state combination of the data states, each data state combination comprising a data state of a memory cell of the first set of memory cells and a data state of a memory cell of the second set of memory cells, each zone of the plurality of zones corresponding to a bit line clamping voltage; and perform a read operation on the selected word line including applying each bit line clamping voltage corresponding to any zones identified.
An apparatus includes a control circuit that is configured to connect to an array of non-volatile memory cells. The control circuit includes a first plurality of data latches configured to connect to non-volatile memory cells of a first plane and a second plurality of data latches configured to connect to non-volatile memory cells of a second plane. The control circuit also includes a shared data transfer data latch configured for transfer of data with the first plurality of data latches and the second plurality of data latches. The shared transfer data latch can be used to transfer data for operations being performed on a first plane to use the data latches on the other plane for storing data for operations on the first plane.
A device structure includes a first dielectric material layer, a first conductive interconnect structure embedded in the first dielectric material layer and including a first metallic barrier liner and a first metal fill material portion having a top surface within a first horizontal plane, where the first metallic barrier liner laterally surrounds the first metal fill material portion and has a top surface below the first horizontal plane such that a moat-shaped divot is located between the first metal fill material portion and the first dielectric material layer, a divot-fill dielectric portion located in the moat-shaped divot and contacting the top surface of the first metallic barrier liner, a second dielectric material layer overlying the first dielectric material layer, and a second conductive interconnect structure embedded in the second dielectric material layer and contacting at least a segment of the top surface of the first metal fill material portion.
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
84.
Stage based frequency optimization for area reduction of charge pumps
A stage-based frequency optimization for a charge pump achieves a higher area efficiency by operating different stages of the charge pump at their optimized frequency simultaneously, instead of single common frequency, to obtain greater output strength. A first set of stages uses triple well devices as transfer switches and operates at a first, higher frequency. The first stages supply a second set of stages using high voltage devices as transfer switches and operates at a second, lower frequency. The two set of stages are connected through a frequency transition circuit.
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
85.
THREE-DIMENSIONAL MEMORY DEVICE WITH INTEGRATED CONTACT AND SUPPORT STRUCTURE AND METHOD OF MAKING THE SAME
A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, each including a respective vertical semiconductor channel and a vertical stack of memory elements, a contact via structure contacting a reference electrically conductive layer that is one of the electrically conductive layers, and at least one silicon oxide liner laterally surrounding a cylindrical portion of the contact via structure and contacting a laterally protruding portion of the contact via structure.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
86.
THREE-DIMENSIONAL MEMORY DEVICE WITH INTEGRATED CONTACT AND SUPPORT STRUCTURE AND METHOD OF MAKING THE SAME
A memory device includes a first-tier alternating stack of first insulating layers and electrically conductive layers located over a substrate, a second-tier alternating stack of second insulating layers and second electrically conductive layers overlying the first-tier alternating stack, a memory stack structure vertically extending through the first-tier alternating stack and the second-tier alternating stack, and a first support and contact assembly vertically extending through the first-tier alternating stack and the second-tier alternating stack. The first support and contact assembly includes a first contact via structure contacting an annular top surface of an electrically conductive layer, a first dielectric pillar structure underlying the reference-level electrically conductive layer, and a first-tier dielectric spacer that laterally surrounds the first contact via structure.
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
A memory system comprises a monolithic integration of a NAND die, a MRAM die and one or more control dies positioned in a same semiconductor package for high speed and high density non-volatile data storage. The MRAM die can be operated as a cache for the NAND die or to provide long term data storage for data not cached for the NAND die. In one embodiment, the NAND die comprises a plurality of NAND strings. The MRAM die comprises a MRAM structure. The one or more control dies comprise one or more control circuits for operating the NAND die and the MRAM die.
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
G11C 11/00 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
Technology is disclosed herein for memory device with control circuitry having an efficient floorplan. Control circuitry resides in a control semiconductor die that is bonded to a memory die NAND strings extending in a z-direction. The memory die has bit lines extending across the NAND strings in an x-direction. First column control circuitry is connected to and configured to control a first set of bit lines. Second column control circuitry is connected to and configured to control a second set of bit lines. The second column control circuitry is stacked in an x-direction with the first column control circuitry. The control die also has system control circuitry configured to control the first column control circuitry and the second column control circuitry. The system control circuitry resides in the floorplan beside the stacked column control circuitry to allow for additional routing of electrical connections above the system control circuitry.
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
Technology is disclosed herein for refreshing threshold switching selectors in programmable resistance memory cells in cross-point memory arrays. The Vt of the threshold switching selector may drift over time. The memory system resets the Vt of the threshold switching selectors with a selector refresh operation and uses a separate data refresh operation to refresh data in programmable resistance memory elements. The data refresh operation itself may also refresh the selector. However, the threshold switching selector refresh operation is faster than the data refresh operation. Moreover, the selector refresh operation consumes much less power and/or current then the data refresh operation. The selector refresh operation may thus be performed at a higher rate than the data refresh operation.
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
90.
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING HETEROJUNCTION SOURCE LAYER AND METHOD FOR MANUFACTURING THE SAME
A memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening and including a memory film and a vertical semiconductor channel including a first semiconductor material, and source structure including an interfacial source layer and a primary source layer. The interfacial source layer includes a second semiconductor material that has a different band gap from a band gap of the first semiconductor material and is in contact with an end portion of the vertical semiconductor channel. The primary source layer includes a third semiconductor material that has a different band gap from the band gap of the second semiconductor material, and the primary source layer is in contact with the interfacial source layer.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
91.
TRANSISTOR CIRCUITS INCLUDING FRINGELESS TRANSISTORS AND METHOD OF MAKING THE SAME
A first field effect transistor includes a first active region and a first gate electrode that includes a first semiconductor gate electrode portion and a first metallic gate electrode portion. The first active region includes a first source region and a first drain region that are laterally spaced from each other by a first channel along a first channel direction. The first gate electrode laterally extends along a first gate electrode direction that is perpendicular to the first channel direction. A maximum lateral extent of the first metallic gate electrode portion along the first gate electrode direction is greater than a maximum lateral extent of the first semiconductor gate electrode portion along the first gate electrode direction.
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
A method of making a memory device includes forming an alternating stack of insulating layers and sacrificial material layers, where a silicon oxycarbide liner is interposed between a first sacrificial material layer and a first insulating layer, and the first sacrificial material layer is direct contact with a second insulating layer or a dielectric material layer composed of a silicon oxide material, forming a memory opening through the alternating stack, forming a memory opening fill structure in the memory opening, forming backside recesses by removing the sacrificial material layers selective to the silicon oxycarbide liner, and forming electrically conductive layers in the backside recesses.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
93.
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING INVERTED STAIRCASE AND METHOD OF MAKING THE SAME
A device structure includes an alternating stack of insulating layers and composite layers located over a source layer, where each of the composite layers includes a combination of a respective dielectric material layer and a respective electrically conductive layer, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, where each of the memory opening fill structures includes a respective vertical stack of memory elements and a respective vertical semiconductor channel, and contact via structures vertically extending through a respective subset of the dielectric material layers and the insulating layers in the alternating stack and contacting a horizontal surface of a respective one of the electrically conductive layers in the alternating stack.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
94.
APPARATUS AND METHOD FOR SELECTIVELY REDUCING CHARGE PUMP SPEED DURING ERASE OPERATIONS
An apparatus is provided that includes a plurality of non-volatile memory cells, a charge pump circuit configured to receive a clock signal and provide a plurality of voltages to the non-volatile memory cells, and a control circuit coupled to the non-volatile memory cells and the charge pump circuit. The control circuit is configured to reduce a current consumed by the apparatus by selectively reducing a clock rate of the clock signal depending on a memory operation being performed on the non-volatile memory cells.
A memory device includes an alternating stack of insulating layers and electrically conductive layers, such that a first electrically conductive layer of the electrically conductive layers is in contact with an underlying silicon oxycarbide liner and with an overlying silicon oxycarbide liner, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel and a memory film containing a continuous memory material layer which continuously extends through the entire alternating stack.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
96.
THREE-DIMENSIONAL MEMORY DEVICE AND METHOD OF MAKING THEREOF INCLUDING EXPANDED SUPPORT OPENINGS AND DOUBLE SPACER WORD LINE CONTACT FORMATION
A memory device includes at least one alternating stack of respective insulating layers and respective electrically conductive layers and memory stack structures vertically extending through the at least one alternating stack. A layer contact via structure contacts a top surface of one of the electrically conductive layers, and is laterally surrounded by at least one dielectric spacer, which may include a plurality of dielectric spacers, and optionally by a plurality of dielectric support pillar structures. Additionally or alternatively, the layer contact via structure may comprise a convex surface segment that is adjoined to a straight sidewall segment.
H01L 23/528 - Layout of the interconnection structure
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
97.
THREE-DIMENSIONAL MEMORY DEVICE AND METHOD OF MAKING THEREOF INCLUDING EXPANDED SUPPORT OPENINGS AND DOUBLE SPACER WORD LINE CONTACT FORMATION
A memory device includes at least one alternating stack of respective insulating layers and respective electrically conductive layers and memory stack structures vertically extending through the at least one alternating stack. A layer contact via structure contacts a top surface of one of the electrically conductive layers, and is laterally surrounded by at least one dielectric spacer, which may include a plurality of dielectric spacers, and optionally by a plurality of dielectric support pillar structures. Additionally or alternatively, the layer contact via structure may comprise a convex surface segment that is adjoined to a straight sidewall segment.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
98.
HIGH VOLTAGE FIELD EFFECT TRANSISTORS WITH SUPERJUNCTIONS AND METHOD OF MAKING THE SAME
A field effect transistor includes a semiconductor channel having a doping of a first conductivity type, a gate structure overlying the semiconductor channel, a source region and a drain region, a source-side extension region including a source-side-extension plate portion and source-side-extension rail portions that overlie the source-side-extension plate portion, source-side counter-doped rails having a doping of the first conductivity type, a drain-side extension region including a drain-side-extension plate portion and drain-side-extension rail portions that overlie the drain-side-extension plate portion, and drain-side counter-doped rails interlaced with the drain-side-extension rail portions. A first superjunction structure is provided between the source-side counter-doped rails and the source-side extension region. A second superjunction structure is provided between the drain-side counter-doped rails and the drain-side extension region.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
Technology is disclosed herein for a memory device with multiple dies bonded together. The memory device may be referred to herein as an integrated memory assembly. The integrated memory assembly has a control semiconductor die and two or more memory semiconductor dies. In one embodiment, each memory semiconductor die has a memory structure having blocks of memory cells. Bit lines extend over the respective memory structure. In one embodiment the integrated memory assembly has what is referred to herein as a “separate bit line architecture”. The separate bit line architecture allows the control semiconductor die to control a memory operation in parallel in the two memory semiconductor dies. Moreover, the separate bit line architecture allows for good scaling of a memory device with multiple dies bonded together.
G11C 16/28 - Sensing or reading circuitsData output circuits using differential sensing or reference cells, e.g. dummy cells
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
100.
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING ETCH STOP STRUCTURES FOR WORD LINE CONTACTS AND METHODS OF EMPLOYING THE SAME
A device includes an alternating stack of insulating layers and electrically conductive layers extending along a first horizontal direction through a first memory array region and a staircase region, where the alternating stack comprises stepped surfaces in the staircase region, vertical stacks of at least one insulating plate and at least one spacer material plate, where each of the vertical stacks is located on a respective horizontal surface segment of the stepped surfaces in the staircase region, a dielectric material portion located in the staircase region having a stepped bottom surface and contacting each of the vertical stacks, and layer contact via structures located in the staircase region and vertically extending through the dielectric material portion and a respective vertical stack of the vertical stacks and contacting a respective one of the electrically conductive layers.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
patents
