A device is configured to receive a first carrier signal, and deliver a second carrier signal, and has a phase-locked loop including a first domain including an oscillator configured to generate a signal at a given frequency, and a circuit configured to generate information representative of the frequency of the signal generated by the oscillator, and to generate the second carrier signal and a clock signal, the first domain being clocked by the first carrier signal, a second domain, clocked by the clock signal, including a circuit configured to compare the frequency of the signal generated by the oscillator with the frequency of the first carrier signal and to control the oscillator, a matching circuit configured to transfer information representative of the frequency of the signal generated by the oscillator from the first domain to the second domain.
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
The present disclosure relates to an electronic device comprising a wafer comprising a first upper surface having at least one first contact arranged thereon; and at least one die comprising a second upper surface having at least one second contact arranged thereon, and at least one first lateral surface orthogonal to the second upper surface, said first contact being coupled to said second contact by a connector comprising one first conductive pillar formed on said first contact of said wafer; one second conductive pillar formed on said second contact of said die; and at least one conductive ball positioned in contact with at least a first upper portion of said first pillar(s) and in contact with at least one second upper portion of said second pillar(s).
H05K 3/30 - Assembling printed circuits with electric components, e.g. with resistor
H05K 3/34 - Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
H05K 3/40 - Forming printed elements for providing electric connections to or between printed circuits
3.
METHOD FOR CONTROLLING AN ANALOG-TO-DIGITAL CONVERTER
The present description provides for a method of controlling an analog-to-digital converter. In an example method, the most significant bits are determined by successive approximations. Further, least significant bits are determined by a time-to-digital conversion by applying a first ramp to the output of a first digital-to-analog converter with a third digital-to-analog converter and by applying a second ramp to the output of the second digital-to-analog converter with a fourth digital-to-analog converter. The variation direction of the first and second ramps is determined by the comparison of the outputs of the first digital-to-analog converter and second digital-to-analog converter at the end of the successive approximations.
The present disclosure relates to an NFC device configured for wireless power transfer, the NFC device comprising an antenna, a frontend circuit coupled to the antenna, a microcontroller coupled to the frontend circuit, the microcontroller comprising an analog-to-digital converter. The analog-to-digital converter is configured to receive an analog amplitude and/or phase signal from the frontend circuit, and to convert the analog signal into a digital signal. The microcontroller is configured to process the digital signal in order to detect a variation in the amplitude and/or phase of the analog signal, so as to detect a change of impedance within the field of the NFC device.
H02J 50/60 - Circuit arrangements or systems for wireless supply or distribution of electric power responsive to the presence of foreign objects, e.g. detection of living beings
H02J 50/20 - Circuit arrangements or systems for wireless supply or distribution of electric power using microwaves or radio frequency waves
H02J 50/80 - Circuit arrangements or systems for wireless supply or distribution of electric power involving the exchange of data, concerning supply or distribution of electric power, between transmitting devices and receiving devices
In an embodiment a switch includes a first MOS transistor having its source connected to its channel-forming region and coupled with a first terminal of the switch, its drain coupled with a second terminal of the switch, and its gate connected to a first node of the switch, a diode coupling the first terminal with the first node, a capacitive element coupling a third terminal of the switch with the first node, the third terminal being configured to receive a control signal for the switch and a discharge circuit coupling the first node with the first terminal, the discharge circuit configured to conduct only when a voltage between the first node and the first terminal is greater than or equal to a threshold.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H03K 17/10 - Modifications for increasing the maximum permissible switched voltage
H03K 17/22 - Modifications for ensuring a predetermined initial state when the supply voltage has been applied
An electronic circuit includes an upper substrate and a lower substrate. An electronic integrated circuit chip is positioned between the upper and lower substrates. The chip includes contact elements coupled to the upper substrate. A first region made of a first material is arranged between the chip and a heat transfer area crossing the lower substrate. A second region filled with a second material couples the lower and upper substrates and laterally surrounds the first region. The first material has a thermal conductivity greater than a thermal conductivity of the second material.
The present disclosure is directed to a light-signal communication receiver device including a photo-receiving diode configured to generate a current signal on a first node from a received light signal, a preamplifier configured to convert the current signal on the first node into a voltage signal on a second node, and a differential amplifier including a first input connected to the first node and a second input connected to a third node coupled to the second node via an adjustment circuit. The adjustment circuit is configured to offset the level of the voltage signal of the second node, on the third node, in a controlled manner by a control signal.
In an embodiment an electronic device includes a first electronic circuit having a capacitive element with a variable capacitance, wherein the first electronic circuit is configured to couple the capacitive element to an antenna, to measure, by successive iterations, a first analog signal representative of a variation of an instantaneous electric power received by the antenna or representative of the instantaneous electric power received by the antenna and to modify the capacitance of the capacitive element until an amplitude of the instantaneous electric power received by the antenna is a maximum, wherein the antenna is configured to capture an amplitude-modulated electromagnetic field.
A method includes receiving a histogram output from a detector sensor, and calculating a median point of a pulse waveform within the histogram. The pulse waveform has an even probability distribution over at least one quantization step of the histogram around the median point. A corresponding apparatus can include a detector sensor and a co-processor coupled to the detector sensor.
In an embodiment, a radio frequency (RF) receiver circuit includes a main circuit and a wake-up circuit. The main circuit is configured to process RF signals. The wake-up circuit is configured to detect a reception of the RF signals. The wake-up circuit includes an automatic gain control (AGC) loop, and is configured to have a first operating mode where a set point voltage of the loop has a first substantially constant value, and a second operating mode where the set point voltage of the loop has a second value dependent on a power supply voltage of the wake-up circuit.
A system to sanitize a surface includes an emitter. The emitter of the system to sanitize the surface includes: a light source configured to generate light at a sanitizing wavelength; a receiver configured to receive a wireless signal; and a processing circuit for the emitter configured to turn the light source on, turn the light source off, and adjust an intensity of light generated by the light source depending on the wireless signal. The system to sanitize the surface further includes a sensor. The sensor of the system to sanitize the surface includes: a photoelectric transducer configured to convert light at the sanitizing wavelength to a current; and a processing circuit for the sensor powered by the current and in communication with a transmitter to transmit the wireless signal, the processing circuit for the sensor being configured to control emission of the wireless signal depending on a power level supplied by the current.
G08B 7/06 - Signalling systems according to more than one of groups Personal calling systems according to more than one of groups using electric transmission
G08C 17/02 - Arrangements for transmitting signals characterised by the use of a wireless electrical link using a radio link
A band-gap circuit for generating a bandgap reference signal includes a first bipolar transistor and a second bipolar transistor of a same type among PNP and NPN types. The first and second bipolar transistors are configured to generate a current varying proportionally with the temperature. A capacitor is connected between a base and an emitter of one or both of the first and second bipolar transistors.
A support substrate supports an electronic chip. An encapsulation coating on the support substrate coats the electronic chip. The encapsulation coating includes a trench surrounding the electronic chip. A heat sink is mounted to the encapsulation coating above the electronic chip. The heat sink is fixed to the encapsulation coating by an adhesive material and a thermal interface material layer is present between the electronic chip and the heat sink. The trench is positioned between the thermal interface material layer and the adhesive material.
STMICROELECTRONICS RESEARCH & DEVELOPMENT) LIMITED (United Kingdom)
Inventor
Raynor, Jeffrey M.
Moeneclaey, Nicolas
Abstract
The present disclosure relates to a sensor having pixels, each pixel having photodiodes having each a terminal coupled to a first node associated with the photodiode; and an amplifier having a first part and, for each photodiode, a second part associated with the photodiode. The first part includes an output of the amplifier and a first MOS transistor of a differential pair. Each second part includes a second MOS transistor of the differential pair having its gate coupled to the first node associated with the photodiode the second part is associated with; a first switch coupling a source of the second transistor to the first part of the amplifier; and a second switch coupling a drain of the second transistor to the first part of the amplifier.
COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES (France)
STMICROELECTRONICS (GRENOBLE 2) SAS (France)
STMicroelectronics (Crolles 2) SAS (France)
Inventor
Mulin, Raphael
Jeannin, Olivier
Deneuville, Francois
Abstract
The disclosure relates to an optoelectronic device comprising in a stack: one reflection polarizing filter, one phase-shifting element configured to add a π/4 phase shift in polarization, one active region, one reflector, so that the light radiation rays reflected by the reflector and passing through the phase-shifting element exhibit a new polarization phase-shifted by π/2 with respect to their initial polarization, the rays then being reflected anew by the polarizing filter in the direction of the active region.
An example computer system includes at least two processors, a power supply controller, configuration registers, and a wake-up circuit. The computer system has a deep sleep mode in which the processors are not supplied with power. The power supply controller is configured to detect events of different types to be processed in the processors in the deep sleep mode. The configuration registers are configured to assign the processing to the different processors according to the type of event detected. The wake-up circuit is configured to disable deep sleep mode after an event is detected, and activate, when disabling deep sleep mode, a power supply of one of the at least two processor to which the processing of the detected event has been assigned according to the configuration registers. The activation of the power supply powering on one of the processors, which is configured to process the detected event.
An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.
In an embodiment an envelope detection device includes an input terminal configured to receive an amplitude-modulated radio frequency signal, a first resistive element and a first MOS transistor connected in parallel between the input terminal and a first node configured to receive a reference potential, a first capacitive element connected between a gate of the first MOS transistor and the first node, an envelope detection circuit connected to the input terminal and configured to supply a voltage representative of an envelope of the amplitude-modulated signal and a circuit for controlling the first MOS transistor configured to supply a first current to the gate of the first MOS transistor only when the voltage is smaller than a first threshold and draw a second current from the gate of the first MOS transistor only when the voltage is higher than a second threshold, the second threshold being higher than the first threshold.
An output potential level among two first levels is delivered according to an input level among two second levels. The output potential level is delivered at a first node connecting together first and second transistors electrically in series between two second nodes of application of the first levels. A first DC voltage defining a high limit for the control voltage of the first transistor is delivered by a first voltage generator powered by one of the second nodes. A second DC voltage defining a high limit for the control voltage of the second transistor is delivered by a second voltage generator controlled by a value representative of the first voltage and powered between the second nodes.
G09G 3/3225 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only
The present disclosure relates to a method wherein a state of an integrated circuit between a first state (e.g., CLOSED), allowing a reading access to the first area of fuse-type non-volatile memory by a processor, and a second state (e.g., OPEN), forbidding the reading access to the memory to the processor, is conditioned to a verification, by a finite state machine, of values of a first fuse word of the memory, representative of a number of transitions to the first state and of a second fuse word of the memory, representative of a number of transitions to the second state.
The present disclosure relates to an USB PD-type interface including a first node receiving a first potential, a second node delivering a second potential, and a third node at a reference potential; a resistor connected between a fourth node coupled to the first node, and a fifth node; a MOS transistor connected between the fifth node and the second node; a bipolar transistor having a collector connected to a gate of the MOS transistor and an emitter connected to the fourth node or the fifth node; and a circuit configured to deliver a control potential to a base of the bipolar transistor determined from a current in the first resistor.
In accordance with embodiments, methods and systems for utilizing multiple threshold checkers are provided. A range sensor collects measurement data. The range sensor examines the measurement data based on multiple threshold checkers to determine satisfaction of a trigger condition. In response to the satisfaction of the trigger condition, the range sensor provides the measurement data to a host computing device of the range sensor.
G06F 1/3231 - Monitoring the presence, absence or movement of users
G01S 7/41 - Details of systems according to groups , , of systems according to group using analysis of echo signal for target characterisationTarget signatureTarget cross-section
G01S 13/56 - Discriminating between fixed and moving objects or between objects moving at different speeds for presence detection
23.
Electronic device comprising surface-mount device type dipoles, and corresponding assembly method
A base substrate has a thickness between two faces. The base substrate includes at least one hole extending in a thickness of the base substrate perpendicular to one of the two faces. At least one dipole of a surface-mount device type is housed in the at least one hole of the base substrate.
An electronic circuit includes image acquisition cells, wherein each cell has a photodetector coupled to a first node of the cell, and an amplifying transistor having a gate connected to the first node, a conduction node coupled to an output of the cell, and a node for controlling a back gate voltage. The amplifying transistor is configured so that its threshold voltage varies according to the back gate voltage. A control circuit adjusts a voltage applied to the control node of the back gate voltage of the amplifying transistor of one of the cells according to a comparison of the voltage present at the cell output and a reference voltage.
H04N 25/616 - Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
A method includes: receiving data signals from a plurality of pixels of an array of pixels; generating a plurality of signal-to-noise ratios by determining signal-to-noise ratios for each respective pixel of the plurality of pixels on the basis of the data signals received from the respective pixel; and filtering the data signals received from each pixel of the plurality of pixels by using an adaptive filter configured on the basis of the plurality of the signal-to-noise ratios to generate filtered data signals.
The present description concerns a derivative measurement circuit. The circuit implements successive cycles, each corresponding to a succession of first, second, and third periods of a clock signal. At each first period, an input voltage is memorized on a first capacitive element and the circuit delivers a voltage indicating a difference between a voltage on a second capacitive element and a voltage on a third capacitive element. At each second period, the input voltage is memorized on the second capacitive element and the circuit delivers a voltage indicating a difference between a voltage on the first capacitive element and the voltage on the third capacitive element. At each third period, the input voltage is memorized on the third capacitive element and the circuit delivers a voltage indicating a difference between the voltage on the second capacitive element and the voltage on the first capacitive element.
H03K 3/023 - Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
G01R 15/16 - Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks using capacitive devices
27.
Package for an integrated circuit and manufacturing method
An encapsulation hood is fastened onto electrically conductive zones of a support substrate using springs. Each spring has a region in contact with an electrically conductive path contained in the encapsulation hood and another region in contact with a corresponding one of the electrically conductive zones. The fastening of the part of the encapsulation hood onto the support substrate compresses the springs and further utilizes a bead of insulating glue located between the compressed springs.
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/10 - ContainersSeals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
H01L 23/12 - Mountings, e.g. non-detachable insulating substrates
A method includes counting a first set of photons having a time-of-flight that falls within a first time range and being detected during a first time period, determining a second time range based on the first set of photons, the second time range being smaller than the first time range, counting a second set of photons having a time-of-flight that fall within the second time range and being detected during a second time period, and determining a third time range based on the second set of photons, the third time range being smaller than the second time range.
A device includes a first AND logic gate comprising a first input, a second input, and an output, a second AND logic gate comprising a first input, a second input, and an output, and a first OR logic gate comprising a first input coupled to the output of the first AND logic gate and a second input coupled to the output of the second AND logic gate. A first selection circuit has first and second data inputs, a first control input coupled to the first input of the first AND logic gate and a second control input coupled to the first input of the second AND logic gate. A first D latch includes a data input coupled to an output of the first selection circuit and an activation input coupled to an output of the first OR logic gate and a second D latch includes a data input coupled to the output of the first selection circuit and an activation input coupled to the output of the first OR logic gate.
H03K 19/173 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components
The present disclosure relates to an NFC device configured for wireless power transfer, the NFC device comprising an antenna, a frontend circuit coupled to the antenna, a microcontroller coupled to the frontend circuit, the microcontroller comprising an analog-to-digital converter. The analog-to-digital converter is configured to receive an analog amplitude and/or phase signal from the frontend circuit, and to convert the analog signal into a digital signal. The microcontroller is configured to process the digital signal in order to detect a variation in the amplitude and/or phase of the analog signal, so as to detect a change of impedance within the field of the NFC device.
H02J 50/60 - Circuit arrangements or systems for wireless supply or distribution of electric power responsive to the presence of foreign objects, e.g. detection of living beings
H02J 50/20 - Circuit arrangements or systems for wireless supply or distribution of electric power using microwaves or radio frequency waves
H02J 50/80 - Circuit arrangements or systems for wireless supply or distribution of electric power involving the exchange of data, concerning supply or distribution of electric power, between transmitting devices and receiving devices
31.
ELECTRONIC CIRCUIT COMPRISING A REFERENCE VOLTAGE CIRCUIT AND A START CHECK CIRCUIT
An electronic circuit includes a reference voltage circuit and a circuit for checking the starting operation of the reference voltage circuit. The reference voltage circuit includes a first stack of a first transistor and second transistor receiving first and second control signals, respectively. The start check circuit includes a first elementary test circuit including a second stack of a third transistor and fourth transistor receiving the first and second control signals, respectively. An output of the first elementary test circuit delivers a first binary signal indicative of proper starting operation of the reference voltage circuit.
The present disclosure relates to a DAC that includes: a first pixel including a first transfer gate coupling a memory node of the first pixel and a capacitive sensing node (SN); a second pixel comprising a first transfer gate coupling a memory node of the second pixel and the capacitive SN; a reset transistor coupling the sensing node to a first voltage supply rail; and a control circuit configured to store electrical charge by activating the reset transistor to apply a reference voltage to the memory node of each of the first and second pixels; and generate a voltage of the DAC at the sensing node by deactivating the reset transistor and controlling the first transfer gates of the first and second pixels to transfer the charge stored.
A differential comparator circuit includes a voltage amplifier of negative gain receiving an analog input signal and generating an inverted analog input signal. The analog input signal and the inverted analog input signal form differential analog input signals. A comparator input circuit includes a first capacitive divider to generate a first signal as an average of the analog input signal and a first ramp signal, and a second capacitive divider to generate a second signal as an average of the inverted analog input signal and a second ramp signal, with the first and second ramp signals being differential ramp signals. The comparator is configured to compare the first and second signals to generate a signal transition having a timing based on the input signal.
H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
H03M 1/56 - Input signal compared with linear ramp
H04N 25/772 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters
H04N 25/778 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself
34.
OPTOELECTRONIC DEVICE WITH TIME-OF-FLIGHT SENSOR USING DYNAMIC TIME WINDOWS
In an embodiment, an optoelectronic device includes a light source and an array of pixels. Each pixel of the array is configured to detect an amount of return light falling in each of a subset of time intervals that form a detection time window of the pixel. A time window position code generator is configured to generate a sequence of time window position codes. Each pixel includes a memory configured to store a first reference time window position associated with the pixel, a time window code comparator configured to compare a first time window position code of the sequence with the first reference time window position, and a timing sequence generator configured to generate, when the comparison indicates a match, a time window control signal configured to activate the detection of the return light during a detection time window selected by the time window control signal.
A method comprises, for each pixel of a depth map, acquiring samples and calculating a distance, and defining a window of N*N pixels with this image pixel at the center, N being an odd integer equal to or greater than 3, and, for each window, classifying the pixels of the window into groups, based on a threshold and distances calculated, calculating for each group, a number of pixels in the group, a confidence factor of the group equal to a sum of the confidence factors of the pixels each determined from the samples acquired for the pixel, and scanning the window from the central pixel by comparing, for each pixel, the confidence factor of the group of the pixel with a threshold and the number of pixels of the group of the pixel with another threshold, and determining whether the central pixel is retained, replaced or discarded.
G06V 10/74 - Image or video pattern matchingProximity measures in feature spaces
G06V 10/764 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using classification, e.g. of video objects
A display includes a display panel and a circuit. The circuit controls the display panel according to at least one control mode such as a pulse width modulation control mode. A method for determining a state of the display includes: acquiring samples from a channel of an ambient light sensor disposed below the display panel; supplying the samples to a processing circuit; detecting, by the processing circuit and based on said samples, whether the display panel is controlled in pulse width modulation; and following detecting the pulse width modulation control mode, calculating by the processing circuit a duty cycle from the samples.
G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
G09G 3/3208 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
An embodiment light sensor includes an array of pixels arranged in rows and in columns. Each pixel comprises a photodiode, a sense node coupled to the photodiode, and an initialization transistor connected to the sense node. N successive pixels of a column or of a row are associated, where N is greater than or equal to 2. The initialization transistor of a first one of the pixels arranged at one end of the association of the N pixels is connected between the sense node of the first one of the pixels and a node of application of an initialization potential. For each two successive pixels among the N pixels, the initialization transistor of one of the pixels that is the most distant from the end is connected between the sense nodes of the two pixels.
The present invention relates to a wireless power transmitter (21) comprising: a power transmitter circuit (210) suitable for being electromagnetically coupled to a power receiver circuit (220) of a kitchen appliance (22), the power transmitter circuit being suitable for transferring power to the kitchen appliance; a first NFC device (230) comprising a first NFC antenna (232), the first NFC device being suitable for being electromagnetically coupled to a second NFC device (240) of the kitchen appliance; the first NFC device being connected to the power transmitter circuit and comprising a wake-up circuit (234) suitable for: periodically transmitting an NFC signal, via the first NFC antenna, during a standby mode of the first NFC device; and detecting a change in the impedance of the first NFC antenna during the standby mode; and, when a change in impedance is detected, exiting standby mode and entering a second mode in which a call procedure is used to establish NFC communications with the second NFC device.
An integrated circuit package includes an assembly of an electronic integrated circuit chip, an optical element and a support substrate. The support substrate includes a mounting face and has an opening sized and shaped to containing the electronic integrated circuit chip. The optical element includes a connection face connected to the mounting face of the support substrate and is positioned opposite to said opening. The electronic integrated circuit chip is connected to the connection face of the optical element such that the electronic chip is housed in said opening of the support substrate.
In an embodiment, a non-volatile memory device is proposed. The device includes a plurality of local pull-up stages distributed along a group of memory portions in a memory array. Each local pull-up stage includes, for each wordline that extends through the group of memory portions, a corresponding local pull-up transistor of an NMOS type. The local pull-up transistors of each local pull-up are configured to locally decouple the corresponding wordline from a node at a first reference potential in response to a wordline that extends through the group of memory portions being selected, and locally couple the corresponding wordline to the node at the first reference potential in response to all the wordlines that extend through the group of memory portions being deselected to restore locally a deselection voltage on a wordline previously selected.
A package includes a mounting plate having a first part able to dissipate heat and a second part able to transmit and/or receive electrical signals. A cladding houses a first electronic chip and second electronic chip. The first electronic chip has a first semiconductor substrate (giving off, in operation, a first quantity of heat) mounted to the first part of the mounting plate and electrically connected by wires to the second part of the mounting plate. The second electronic chip has a second semiconductor substrate (giving off, in operation, a second quantity of heat) mounted to an interposer support including an interconnection network. An array of connection balls interconnects the interposer support to the first part of the mounting plate and the second part of the mounting plate. The first and second semiconductor substrates are different.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
42.
Electronic chip support device and corresponding manufacturing method
Electronic device comprising a support substrate having a mounting face and an electronic chip having a rear face bonded on the mounting face by a volume of adhesive, wherein the support substrate comprises a plurality of wedging elements projecting from the mounting face so as to hold the chip bearing on contact areas of the wedging elements in a position substantially parallel to the mounting face of the support substrate.
An integrated circuit includes a computer unit configured to execute the neural network. Parameters of the neural network are stored in a first memory. Data supplied at the input of the neural network or generated by the neural network are stored in a second memory. A first barrel shifter circuit transmits data from the second memory to the computer unit. A second barrel shifter circuit delivers data generated during the execution of the neural network by the computer unit to the second memory. A control unit is configured to control the computer unit, the first and second barrel shifter circuits, and accesses to the first memory and to the second memory.
STMicroelectronics Design and Application S.R.O. (Czech Republic)
STMicroelectronics (Alps) SAS (France)
Inventor
Vassal, Robin
Andrle, Jiri
Cabaj, Peter
Trouilleau, Cyrille
Abstract
A method is for detecting one or more objects in a detection zone using a time-of-flight sensor. The method includes emitting optical radiation via the emission circuitry of the sensor and subsequently capturing the reflected optical radiation using the reception circuitry. This captured radiation is quantified in terms of photons, and measurement circuitry determines both the amount of these photons and the distance from the sensor to the object(s). An analysis of the photon count, combined with the calculated distance, is used to determine the presence or absence of objects within the detection zone.
In an embodiment, a USB interface includes a transformer, a primary winding of the transformer, and a first switch in series between a first and a second node, a secondary winding of the transformer and a component in series between a third and a fourth node, the fourth node configured to be set a first reference potential, a second switch connected between the third node and a first terminal, the first terminal configured to provide an output voltage of the USB interface; wherein the component is configured to avoid a current circulation in the secondary winding when the first switch is closed and a control circuit configured to compare a first voltage of an interconnection node between the secondary winding and the component to a first threshold and compare the first voltage to a second threshold when the first voltage is, in absolute values, above the first threshold.
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
H02M 1/32 - Means for protecting converters other than by automatic disconnection
46.
Method for controlling an analog-to-digital converter
The present description concerns a method of controlling an analog-to-digital converter, wherein most significant bits are determined by successive approximations implementing a first digital-to-analog converter and a second digital-to-analog converter. Further, least significant bits are determined by a time-to-digital conversion by applying a first ramp to the output of the first converter with a third digital-to-analog converter and by applying a second ramp to the output of the second converter with a fourth digital-to-analog converter. The variation direction of the first and second ramps is determined by the comparison of the outputs of the first and second converters at the end of the successive approximations.
An optoelectronic device includes a backlight panel illuminating a display panel. The backlight panel includes an array of light emitting pixels, each light emitting pixel having at least one subpixel with one or more light emitting diodes positioned on a substrate. The pixel further includes at least one photodetector positioned on the substrate and arranged to detect an amount of reflected light emitted by said subpixel and reflected by the display panel.
G09G 3/34 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
An integrated circuit includes an electronic chip having a face covered with a thermal interface material layer. A heat sink includes a mounting area fixed to the chip via the thermal interface material layer. The heat sink includes open notches extending into the mounting area to delimit fins separated from each other by the open notches.
An integrated circuit package includes a support substrate and a cover fastened on a first face of the support substrate. The cover and support substrate define a housing containing an electronic integrated circuit chip having a first face equipped with electrically conductive protruding elements. A first space between the cover and a second face of the electronic integrated circuit chip is filled with a first shape memory material in the austenitic state. A second space between each pair of electrically conductive protruding elements and electrically conductive contact pads of the support substrate is filled with a second shape memory material in the austenitic state.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/051 - ContainersSeals characterised by the shape the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body another lead being formed by a cover plate parallel to the base plate, e.g. sandwich type
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
A voltage matching circuit receives a first voltage received by a connector, and outputs a second voltage. The second voltage is equal to the first voltage, if the first voltage is less than a threshold voltage. The second voltage is equal to the first voltage divided by a first factor, if the first voltage is greater than or equal to the threshold voltage.
The present description concerns a package for an electronic device. The package including a plate and a lateral wall, separated by a layer made of a bonding material and at least one region made of a material configured to form in the region an opening between the inside and the outside of the package when the package is heated.
In accordance with an embodiment, a power supply circuit includes: a first transistor device comprising a first gate associated with a first transconductance and a second gate associated with a transconductance greater than the first transconductance; and a second transistor device including a third gate associated with a second transconductance and a fourth gate associated with a transconductance greater than the second transconductance. The second transistor device is configured to supply power to at least one load, the first and the third gates are controlled by a closed regulation loop, and the second and the fourth gates are controlled by a sampled reference voltage.
H04N 25/709 - Circuitry for control of the power supply
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
G05F 3/20 - Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode-transistor combinations
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
H02M 3/155 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
H04N 25/77 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
An integrated circuit package includes at least one electronic chip having a first face fastened onto a first face of a carrier substrate by an adhesive interface. The adhesive interface includes a crown formed of a first adhesive material that is fastened on the periphery of the first face of the electronic chip. The crown defining an internal housing. A second adhesive material, different than the first material, is deposited in the internal housing.
An electronic system includes a control circuit to provide a binary control signal alternating between a first binary state during first phases and a second binary state during second phases; a screen controlled by the control signal, the screen emitting light during each first phase, and to not emit any light during each second phase; a light sensor under the screen or along the edge of the screen, and providing a measurement signal representative of a quantity of light received by the sensor during a measurement phase or a plurality of consecutive measurement phases; and a synchronization device to synchronize each measurement phase with a second phase.
G09G 3/34 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source
A non-conductive encapsulation cover is mounted on a support face of a support substrate to delimit, with the support substrate, an internal housing. An integrated circuit chip is mounted to the support substrate within the internal housing. A metal pattern is mounted to an internal wall of the non-conductive encapsulation cover in a position facing the support face. At least two U-shaped metal wires are provided within the internal housing, located to a side of the integrated circuit chip, and fixed at one end to the metallic pattern and at another end to the support face.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/552 - Protection against radiation, e.g. light
An integrated circuit package includes a cavity within which a circuit device is contained. At least one through hole is provided in at least one wall of the cavity. The at least one through hole includes at least one first portion flaring towards the cavity with a frustoconical shape, for example.
H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
57.
Method and apparatus for processing a histogram output from a detector sensor
A method includes receiving a histogram output from a detector sensor, and calculating a median point of a pulse waveform within the histogram. The pulse waveform has an even probability distribution over at least one quantization step of the histogram around the median point. A corresponding apparatus can include a detector sensor and a co-processor coupled to the detector sensor.
An optical sensor includes pixels. Each pixel has a photodetector. A readout circuit performs a process over an exposure time where the photodetector is connected to a reverse bias voltage supply to reset a voltage across the photodetector, and the photodetector is disconnected from the reverse bias voltage supply until that the voltage across the photodetector decreases in response to received ambient light. An ambient light level is then determine an based on a number of times the voltage across the photodetector is reset over the exposure time.
In an embodiment an electronic circuit includes a first grid configured to be biased with a potential different from ground, the first grid including conductive tracks arranged in a first level of the electronic circuit and conductive tracks arranged in a second level of the electronic circuit, wherein the first grid is configured to power a first circuit at least partially implemented in a level arranged below the first and second levels, and wherein the conductive tracks are arranged in the first level extending along a first direction and being separated from one another by spacings and a conductive rail coupling a first node and a second circuit by crossing the first grid, wherein the conductive rail is insulated from the first grid and configured to be biased with a potential different from the ground, and wherein the conductive rail includes conductive tracks arranged in the first level of the electronic circuit along the first direction and in the spacings of the conductive tracks.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/528 - Layout of the interconnection structure
H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
An optoelectronic device includes a backlight panel illuminating a display panel. The backlight panel includes an array of light emitting pixels, with each light emitting pixel including at least one subpixel formed by one or more light emitting diodes positioned on a substrate. At least one photodetector is positioned on the substrate and arranged to detect an amount of reflected light emitted by said subpixel and reflected by the display panel.
G02F 1/1335 - Structural association of cells with optical devices, e.g. polarisers or reflectors
H01L 31/173 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto the semiconductor device sensitive to radiation being controlled by the light source or sources the light sources and the devices sensitive to radiation all being semiconductor devices characterised by at least one potential or surface barrier formed in, or on, a common substrate
A time-of-flight sensor includes a light emitting device configured to emit light rays toward a scene and a photosensitive pixel matrix configured to receive light signals reflected from the scene and to generate an image that includes dots associated with the light signals reflected from the scene. Each dot covers a number of pixels of the image. A processing unit is configured to, for each dot of the image, partition the pixels of the dot into at least one group of pixels and, for each group of pixels, compute a representative value of distance values of the pixels of this group. The representative distance value can then be applied to each pixel of the group of pixels.
An electronic device includes an electronic chip located between a cover and an interconnection substrate. The electronic chip has contact pads located in front of a first surface of the interconnection substrate. At least one metal region (for example extending on the front surface) thermally couples at least one contact pad of the electronic chip to the cover.
In an embodiment a digital-to-analog converter includes a plurality of first capacitors, each having a first electrode and a second electrode, wherein the second electrodes are connected together and are connected to an inverting input of a first amplifier stage having its non-inverting input coupled to ground, a plurality of first switches, each of the first capacitors having its first electrode connected to a corresponding one of the first switches, wherein each of the first switches is configured to occupy a first state where the first electrode of a corresponding first capacitor is coupled to a first reference voltage and occupy a second state where the first electrode of the corresponding first capacitor is coupled to a second reference voltage different from the first reference voltage, a capacitive feedback circuit connected between the inverting input and an output of the first amplifier stage, the capacitive feedback circuit including at least one second capacitor and a controller.
A method for operating an electronic device includes while a display is in low power mode, detecting based on data collected by a time of flight (ToF) sensor, a movable object within a field of view of the electronic device; in response to the detecting initiating a period of detection having a plurality of frames, the period of detection being a time period over which a distance value indicative of a distance between the movable object and the display is detected; for each of the plurality of frames, changing the distance value to reflect whether the movable object is moving near or further from the electronic device; detecting that the distance value after the period of detection is less than a threshold distance value indicative of the movable object approaching the display; if the distance value is less than the threshold distance value, waking up the display.
An integrated-circuit package includes a flexible electrical-connection element sandwiched between a first face of a first multilayer support substrate and a second face of a second multilayer support substrate. The flexible electrical-connection element laterally projects with respect to, and is in electrical contact with at least one of, the multilayer support substrates. The flexible electrical-connection element and the first multilayer support substrate include, at a first region, respectively two first mutually facing orifices defining together a first cavity. The first cavity is at least partially closed off by a first part of the second face of the second multilayer support substrate. A first component is located in the first cavity, attached at the first part of the second face of the second multilayer support substrate and in electrical contact with the flexible electrical-connection element through the second multilayer support substrate.
H10F 55/20 - Radiation-sensitive semiconductor devices covered by groups , or being structurally associated with electric light sources and electrically or optically coupled thereto wherein the electric light source controls the radiation-sensitive semiconductor devices, e.g. optocouplers
H10F 55/00 - Radiation-sensitive semiconductor devices covered by groups , or being structurally associated with electric light sources and electrically or optically coupled thereto
66.
Electronic device integrating an antenna and method of fabricating such a device
An electronic device integrates an antenna. To fabricate such an electronic device, first antenna elements are formed on a first surface of a first substrate. The first substrate is then diced to form antenna chips. Each antenna chip includes, on a first surface corresponding to the first surface of the first substrate, one of the first antenna elements. One of the antenna chips is then bonded onto a transfer substrate. This bonding is made between a second surface of the antenna chip, orthogonal to its first surface, and an upper surface of the transfer substrate.
An indirect time-of-flight measurement sensor includes a photosensitive pixel array configured to acquire a succession of images of a scene during a given exposure time. The sensor includes a control unit configured to control the acquisition of the succession of images by the pixel array and to define an exposure time for this acquisition based on a pixel saturation rate of the array, distances between the sensor and elements of the scene, and a standard deviation of the distances between the sensor and the elements of the scene.
An embodiment voltage converter includes a first transistor connected between a first node of the converter and a second node configured to receive a power supply voltage, a second transistor connected between the first node and a third node configured to receive a reference potential, a first circuit configured to control the first and second transistors, and a comparator configured to compare a first voltage with a threshold, the first voltage being equal, during a first period, to a first increasing ramp and, during a second period, to a second decreasing ramp, the threshold having a first value during the first period and a second value during the second period, the first and second values being variable.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
In an embodiment an electronic device includes a first electronic circuit having a capacitive element with a variable capacitance, wherein the first electronic circuit is configured to couple the capacitive element to an antenna, to measure, by successive iterations, a first analog signal representative of a variation of an instantaneous electric power received by the antenna or representative of the instantaneous electric power received by the antenna and to modify the capacitance of the capacitive element until an amplitude of the instantaneous electric power received by the antenna is a maximum, wherein the antenna is configured to capture an amplitude-modulated electromagnetic field.
This disclosure relates to a time-of-flight sensor including, on a same base substrate, a light emitter configured to emit light into an image scene, a reference sensor configured to detect light emitted by the light emitter, and a signal reception sensor array separated from the light emitter by an optical barrier. The optical barrier is configured to prevent light emitted by the light emitter from directly reaching the signal reception sensor array, with the signal reception sensor array being configured to detect light reflected by the image scene. The reference sensor and the signal reception sensor array are based on semiconductor nanoparticles.
The image sensor includes an array of photosensitive pixels comprising at least two sets of at least one pixel, control circuit configured to generate at least two different timing signals and adapted to control an acquisition of an incident optical signal by the pixels of the array, and distribution circuit configured to respectively distribute the at least two different timing signals in the at least two sets of at least one sensor, during the same acquisition of the incident optical signal.
H04N 25/46 - Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by combining or binning pixels
H04N 25/583 - Control of the dynamic range involving two or more exposures acquired simultaneously with different integration times
The present disclosure relates to a voltage source device comprising: a voltage converter for generating a supply voltage at an output node of the voltage converter based on a feedback signal provided on a feedback line; at least one switch coupled between the output node of the voltage converter and an output terminal of the voltage source device; and at least one further switch configured to selectively couple the feedback line to: the output node of the voltage converter during a first regulation mode; and to the output terminal of the voltage source device during a second regulation mode.
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
In an embodiment a device includes an input node configured to receive a first current, an output node configured to provide a second current determined by the first current, a first resistor having a first terminal connected to the input node and a second terminal coupled to a first node configured to receive a first supply voltage, a first MOS transistor having a source connected to the first node and a drain coupled to the output node of the device, a second resistor having a first terminal connected to a gate of the first MOS transistor, a biasing circuit configured to provide a biasing voltage on a second terminal of the second resistor and a first capacitor connected between the input node and the gate of the first MOS transistor.
In an embodiment a switch includes a first MOS transistor having its source connected to its channel-forming region and coupled with a first terminal of the switch, its drain coupled with a second terminal of the switch, and its gate connected to a first node of the switch, a diode coupling the first terminal with the first node, a capacitive element coupling a third terminal of the switch with the first node, the third terminal being configured to receive a control signal for the switch and a discharge circuit coupling the first node with the first terminal, the discharge circuit configured to conduct only when a voltage between the first node and the first terminal is greater than or equal to a threshold.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H03K 17/10 - Modifications for increasing the maximum permissible switched voltage
H03K 17/22 - Modifications for ensuring a predetermined initial state when the supply voltage has been applied
76.
Speed measurement using time-of-flight sensing and anti-collision protection using time-of-flight sensing
A measurement of the rotation speed of an object is made using a time-of-flight sensor configured to detect a passing of one or more of elements of the object through a given position. The time-of-flight sensor is further mounted on a one-person vehicle configured to protect the one-person vehicle against collisions through the making a time-of-flight measurement of a relative speed between the one-person vehicle and an obstacle.
B60K 31/00 - Vehicle fittings, acting on a single sub-unit only, for automatically controlling vehicle speed, i.e. preventing speed from exceeding an arbitrarily established velocity or maintaining speed at a particular velocity, as selected by the vehicle operator
An embodiment of the present disclosure relates to a power supply interface comprising: a converter delivering a first DC voltage; a resistor connected between the converter and an output terminal of the interface delivering a second DC voltage; a first circuit delivering a second signal representative of a difference between the second DC voltage and a voltage threshold when a first signal is in a first state, and at a default value otherwise; a second circuit delivering a third signal representative of a value of a current in first resistor multiplied by a gain of the third circuit, and modifying the gain based on the second signal; and a third circuit configured to deliver a signal for controlling the converter based at least on the third signal.
An electronic device includes an electronic chip assembled on a first region of a substrate of the electronic device, a first coating layer of a first coating material covering a surface of the electronic chip facing away from the substrate, and a radiation element of an antenna of the electronic device separated from the substrate by at least a portion of the first coating layer and being offset with respect to the first region of the substrate so that the radiation element does not cover the electronic chip. The radiation element is buried in the first coating layer or is arranged in the first coating layer and partly covered with a protection material.
H05K 3/10 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
An electronic device includes an electronic integrated circuit chip assembled on a first region of a substrate. A radiation element of an antenna is mounted to the substrate in a manner where it is separated from the substrate by a second layer of a second dielectric material, and i\s further offset with respect to the first region of the substrate so that the radiation element does not cover the electronic integrated circuit chip. A first coating layer of a first coating material covers at least a surface of the electronic integrated circuit chip facing away from the substrate further covers a surface of the radiation element facing away from the substrate.
An imaging device includes an array of photosensors. A film of semiconductor nanoparticles is common to the photosensors of the array. The nanoparticles are configured to be excited by light with wavelengths in a range from 280 to 1500 nanometers. Each photosensor includes a top electrode and a bottom electrode positioned on opposite sides of the film of semiconductor nanoparticles. At least some of the photosensors further include a filter configured to transmit light with wavelengths in a range from 280 to 400 nanometers, and to at least partially filter out light with wavelengths greater than 400 nanometers from reaching the photosensor. A transistor level is electrically coupled to the top and bottom electrodes of the photosensors.
H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
81.
Device comprising a synchronization circuit for performing near field communication
A device is configured to receive a first carrier signal, and deliver a second carrier signal, and has a phase-locked loop including a first domain including an oscillator configured to generate a signal at a given frequency, and a circuit configured to generate information representative of the frequency of the signal generated by the oscillator, and to generate the second carrier signal and a clock signal, the first domain being clocked by the first carrier signal, a second domain, clocked by the clock signal, including a circuit configured to compare the frequency of the signal generated by the oscillator with the frequency of the first carrier signal and to control the oscillator, a matching circuit configured to transfer information representative of the frequency of the signal generated by the oscillator from the first domain to the second domain.
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
In an embodiment a computer system includes a display screen, a time-of-flight sensor disposed in a vicinity of the screen and configured to acquire distance information of several zones of a scene facing the screen in a field of view of the time-of-flight sensor and a processor configured to determine a presence of a user of the computer system in the scene, detect a presence of at least one individual other than the user from the distance information acquired by the time-of-flight sensor and inform the user when a presence of the at least one individual other than the user is detected.
An apparatus is for testing a device to be supplied with power via USB Power Delivery (USB-PD). The apparatus includes at least one USB Type-C connector configured to be connected to the device to be supplied with power to be tested, the at least one USB Type-C connector including a power supply terminal. Processing circuitry of the apparatus is configured to verify that a voltage at the power supply terminal is lower than a first threshold, verify a role of the device, generate requests representative of power supply configurations supported by the role of the device, and verify compatibility of the power supply configurations supported by the device with standardized power supply configurations.
In a method, substrate elements are provided wherein each substrate element has a first side and a second side meeting at a corner point. The substrate elements are picked and then placed on a support device in alignment. A cutting operation is then performed where each of the substrates elements are cut along a cut line having a common first direction which intersects the first and second sides of each of the substrate elements in order to create a third side on each substrate element. The third side of each of the substrate elements meets the first and the second sides at corresponding corner points.
B28D 5/00 - Fine working of gems, jewels, crystals, e.g. of semiconductor materialApparatus therefor
B28D 5/04 - Fine working of gems, jewels, crystals, e.g. of semiconductor materialApparatus therefor by tools other than of rotary type, e.g. reciprocating tools
The present disclosure relates to a device comprising a first transimpedance amplifier comprising a first amplification stage with a first MOS transistor, a second transimpedance amplifier comprising a second amplification stage with a second MOS transistor, and a current source series-connected with the first and second amplification stages, the current source having a first terminal coupled to the drain of the first MOS transistor and a second terminal coupled to the drain of the second MOS transistor.
H03F 3/08 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only controlled by light
H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
H03F 1/26 - Modifications of amplifiers to reduce influence of noise generated by amplifying elements
An interconnection substrate includes a thermomechanical support crossed by at least one electric interconnection hole. A first interconnection network is formed on a first surface of the thermomechanical support and a second interconnection network is formed on a second surface of the thermomechanical support. Each interconnection network includes and interconnection level formed by at least one metal track from which at least one metal via extends. The at least one metal track and the at least one metal via are embedded in an insulator layer so that the at least one metal via is flush with a surface of the insulator layer most distant from the thermomechanical support. At least one metal track protrudes from the insulator layer of the last interconnection level. The metal vias are configured to electrically couple together two adjacent levels and/or the last level with the at least one protruding metal track.
H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
87.
Apparatus and method for communication on a serial bus
The present disclosure relates to a method comprising receiving edges conveyed by a serial bus and separated by multiples of a same duration, determining a measurement value of a ratio between a cycle time of a clock and the duration, and sending bits on the serial bus using the measurement value.
An ambient light sensor includes pixels arranged in an array. Each pixel includes a doped insulated well of a first type, a pinned photodiode in the well, a doped region of a second type arranged in the well, a transfer gate coupling the photodiode to said region, and a first circuit applying a first or second potential to the well. A successive approximation analog-to-digital converter of the sensor has a node connected to the doped regions of the pixels, a switch applying a third potential to the node, a comparator coupled to the node, and a second circuit receiving an output of the comparator and controlling the first circuits to selectively apply the first and second potentials. A sensor control circuit controls the gates and the first switch.
A time-of-flight sensor includes a first light ray generation circuit and a second light ray reception circuit. A resin layer encapsulates the first light ray generation circuit and the second light ray reception circuit. A first region configured to emit light rays of the first light ray generation circuit is exposed at a surface of the resin layer. A second region configured to receive light rays of the second light ray reception circuit is also exposed at that surface of the resin layer. The surface of the resin layer is configured to be directed towards a scene.
G01S 7/481 - Constructional features, e.g. arrangements of optical elements
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
90.
Chip containing an onboard non-volatile memory comprising a phase-change material
An integrated circuit includes a substrate with an active area, a first insulating layer, a second insulating layer, and a phase-change material. The integrated circuit further includes a heating element in an L-shape, with a long side in direct physical contact with the phase-change material and a short side in direct physical contact with a via. The heating element is surrounded by first, second, and third insulating spacers, with the first insulating spacer having a planar first sidewall in contact with the long side of the heating element, a convex second sidewall, and a planar bottom face in contact with the short side of the heating element. The second and third insulating spacers are in direct contact with the first insulating spacer and the long side of the heating element.
An imaging device includes a first layer made of quantum dots and a second layer including at least two filter regions extending over the first layer. The at least two filter regions are configured to transmit distinct wavelengths. The quantum dots of the first layer are configured to generate charges upon reception of light in the distinct wavelengths.
In accordance with an embodiment, a video flow transmission method includes: the generating, by an image sensor, a video flow comprising first and second images; hashing, by the image sensor, a portion of the first image based on a first hashing configuration to generate a first hash value, the first hashing configuration defining first positions of pixels to be hashed; hashing, by the image sensor, a portion of the second image based on a second hashing configuration to generate a second hash value, the second hashing configuration being different from the first configuration and defining second positions of pixels to be hashed; and transmitting, by the image sensor, the first and second images, and the first and second hash values, to a second device.
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
93.
Electronic device comprising a carrier substrate and an encapsulating cover mounted on the carrier substrate, and corresponding mounting process
A carrier substrate is configured to carry at least one electronic chip and includes a mounting front face. An encapsulating cover is mounted on the front face of the carrier substrate through a mounting. This mounting includes at least one seating surface through which the cover and the carrier substrate make contact. At least one adhesive bead is located elsewhere than the seating surface in order to securely fasten the encapsulation cover and the carrier substrate.
H10F 55/10 - Radiation-sensitive semiconductor devices covered by groups , or being structurally associated with electric light sources and electrically or optically coupled thereto wherein the radiation-sensitive semiconductor devices control the electric light source, e.g. image converters, image amplifiers or image storage devices
A first integrated circuit chip is assembled to a second integrated circuit chip with a back-to-back surface relationship. The back surfaces of the integrated circuit chips are attached to each other using one or more of an adhesive, solder or molecular bonding. The back surface of at least one the integrated circuit chips is processed to include at least one of a trench, a cavity or a saw cut.
Described herein is a time-of-flight ranging system and methods for its operation. The system includes an array of single photon avalanche diode (SPAD) pixels and control circuitry. The control circuitry simultaneously accumulates integrated SPAD event data from one cluster of SPAD pixels while integrating SPAD event data from another cluster during different target illuminations. The system also includes first and second VCSEL clusters, each responsible for a different target illumination. By processing and managing the data in this manner, the system can effectively reduce the time used to gather and analyze the event data, leading to faster and more accurate distance measurements.
G01S 7/4914 - Detector arrays, e.g. charge-transfer gates
G01S 7/4865 - Time delay measurement, e.g. time-of-flight measurement, time of arrival measurement or determining the exact position of a peak
G01S 17/36 - Systems determining position data of a target for measuring distance only using transmission of continuous waves, whether amplitude-, frequency-, or phase-modulated, or unmodulated with phase comparison between the received signal and the contemporaneously transmitted signal
H01L 31/107 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode
96.
DEVICE WITH COMMAND LIST EXECUTION AND RELATED METHOD
A device includes an application processor and a hardware signal processor coupled to the application processor. The hardware signal processor, in operation: receives a command pre-list during an initialization phase of the hardware signal processor, the command pre-list including a plurality of function describers, each of the plurality of function describers being associated with a respective plurality of parameter describers; generates a command list based on the command pre-list during the initialization phase; and stores the command list in memory circuitry.
According to one aspect, the invention provides a computer system comprising: - at least two processors (P1, P2), the computer system (SYS) having a deep sleep mode in which the processors are not supplied with power; - a power supply controller (PCTRL) configured to detect events of different types that require processing by the at least two processors (P1, P2) when the computer system is in deep sleep mode; - configuration registers (WCFG) allowing the processing of each detected event to be assigned to the different processors according to the type of event detected; - a wake-up circuit (WKUC) configured to disable deep sleep mode after an event is detected by the power supply controller (PCTRL), the wake-up circuit (WKUC) being configured to activate a power supply of the processor (P1, P2) to which the processing of the detected event has been assigned according to the configuration registers, said processor (P1, P2) subsequently being configured to process the detected event.
The present disclosure is directed to a light-signal communication receiver device including a photo-receiving diode configured to generate a current signal on a first node from a received light signal, a preamplifier configured to convert the current signal on the first node into a voltage signal on a second node, and a differential amplifier including a first input connected to the first node and a second input connected to a third node coupled to the second node via an adjustment circuit. The adjustment circuit is configured to offset the level of the voltage signal of the second node, on the third node, in a controlled manner by a control signal.
An electronic system includes a first LC oscillator connected to a first general-purpose input/output (GPIO) circuit and a second LC oscillator connected to a second GPIO circuit. A threshold generator is coupled to an input of the comparator. A control circuit is configured to control a measurement phase comprising a first capture phase and a second capture phase. A microcontroller is coupled to the control circuit and a power management circuit is configured to switch-off the microcontroller following activation of the control circuit by the microcontroller. The control circuit is configured to control the application of an excitation signal to the each oscillator via the respective GPIO circuit, control the GPIO circuit so that oscillations of the oscillator are provided to the comparator, and count, based on an output of the comparator, a number of oscillations in the oscillator exceeding a threshold output by the threshold generator.
G01B 7/30 - Measuring arrangements characterised by the use of electric or magnetic techniques for measuring angles or tapersMeasuring arrangements characterised by the use of electric or magnetic techniques for testing the alignment of axes
H03B 5/08 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
100.
Memory architecture of a near-field communication device
A near-field communication device operates to transmit data by near-field communications techniques to another device. The near-field communication device includes a memory that stores a message to be transmitted in an ASCII format. The message is retrieved from the memory and transmitted using the near-field communications techniques in an ASCII format.
G06K 7/10 - Methods or arrangements for sensing record carriers by electromagnetic radiation, e.g. optical sensingMethods or arrangements for sensing record carriers by corpuscular radiation
G08C 15/06 - Arrangements characterised by the use of multiplexing for the transmission of a plurality of signals over a common path successively, i.e. using time division
H04B 5/72 - Near-field transmission systems, e.g. inductive or capacitive transmission systems specially adapted for specific purposes for local intradevice communication
H04W 88/18 - Service support devicesNetwork management devices
H04W 4/80 - Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
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