A semiconductor chip has a top metal layer with a passivation over an outer surface and including a first region and a second region. The passivation is fully removed from the first region and a contact layer for electrical wafer sorting probes is formed over the first region having the passivation fully removed therefrom. The passivation is initially only partly removed from the second region to protect the top met layer. Later, a remaining portion of the passivation is fully removed at the second region. Then, top metal layer at the second region provides a growth region for growing electrically conductive material over the second region.
Semiconductor chips to be singulated to individual semiconductor devices are arranged onto respective adjacent areas of a mounting substrate such as a pre-molded leadframe. The mounting substrate is made of a laminar, electrically conductive sculptured structure with molded electrically insulating material. Electrically conductive side formations in the adjacent areas of the mounting substrate include first and second pads at front and back surfaces, respectively, of the mounting substrate. The first contact pads at the front surface of the substrate include narrowed portions having side recesses. The second contact pads at the back surface of the substrate include widened portions having side extensions adjacent the side recesses. The electrically insulating material extends into the side recesses to provide anchoring formations of the insulating material to the electrically conductive sculptured structure of the mounting substrate.
Semiconductor chips are arranged on an elongated substrate and encapsulated by an insulating encapsulation. Electrically conductive formations and electrically conductive plating lines are plated on the insulating encapsulation using, for example, Laser Direct Structuring (LDS) or Direct Copper Interconnect (DCI) material. The electrically conductive plating lines include first transverse plating lines as well as second plating lines branching out from the first plating lines towards the electrically conductive formations. A first partial cutting step is then performed to form grooves which remove the first plating lines. An insulating material is dispensed in the grooves to encapsulate the end portions of the second plating lines. A second cutting step median along the groove and through the elongate substrate is performed to produce singulated semiconductor devices (such as “die pad up” Quad-Flat No-lead (QFN) packages). End portions of the second plating lines are encapsulated by the insulating material.
A PWM signal generator circuit includes a multiphase clock generator that generates a number n of phase-shifted clock phases having the same clock period and being phase shifted by a time corresponding to a fraction 1/n of the clock period. The PWM signal generator circuit determines for each switch-on duration first and second integer numbers, and for each switch-off duration third and fourth integer numbers. The first integer number is indicative of the integer number of clock periods of the switch-on duration and the second integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-on duration. The third integer number is indicative of the integer number of clock periods of the switch-off duration, and the fourth integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-off duration.
The disclosure is directed to wide band-gap semiconductor devices, such as power devices based on silicon carbide or gallium nitride materials. A power device die is attached to a carrier substrate or a base using sintered silver as a die attachment material or layer. The carrier substrate is, in some embodiments, copper plated with silver. The sintered silver die attachment layer is formed by sintering silver nanoparticle paste under a very low temperature, for example, lower than 200° C. and in some embodiments at about 150° C., and with no external pressures applied in the sintering process. The silver nanoparticle is synthesized through a chemical reduction process in an organic solvent. After the reduction process has completed, the organic solvent is removed through evaporation with a flux of inert gas being injected into the solution.
B22F 9/24 - Making metallic powder or suspensions thereofApparatus or devices specially adapted therefor using chemical processes with reduction of metal compounds starting from liquid metal compounds, e.g. solutions
In an electronic device, a pulse generator receives an input signal and a clock signal and produces a transmission signal that includes a pulse following each edge of the input signal and of the clock signal. The pulse is low when the input signal is low and high when the input signal is high. A transmitter produces, at its two output nodes, a replica of the transmission signal and the complement of the transmission signal. A galvanic isolation barrier is coupled to the output nodes of the transmitter and produces a differential signal that includes a positive spike at each rising edge of the transmission signal and a negative spike at each falling edge of the transmission signal.
H03K 17/605 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being bipolar transistors with galvanic isolation between the control circuit and the output circuit
H03K 5/133 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active-delay devices
H03K 19/096 - Synchronous circuits, i.e. using clock signals
7.
INTEGRATED CIRCUIT CHIP PACKAGE THAT DOES NOT UTILIZE A LEADFRAME
An integrated circuit die includes a semiconductor substrate, an interconnect layer including bonding pads, and a passivation layer covering the interconnect layer and including openings at the bonding pads. A conductive redistribution layer including conductive lines and conductive vias is supported by the passivation layer. An insulating layer covers the conductive redistribution layer and the passivation layer. Channels formed in an upper surface of the insulating layer delimit pedestal regions in the insulating layer. A through via extends from an upper surface of each pedestal region through the pedestal region and the insulating layer to reach and make contact with a portion of the conductive redistribution layer. A metal pad is formed at the upper surface of each pedestal region in contact with its associated through via. The metal pads for leads of a quad-flat no-lead (QFN) type package.
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
A wafer-level package includes an integrated circuit (IC) die with pads on its front side. Surrounding the die's edge sides and front side is a resin layer containing an activatable catalyst material. A first passivation layer is positioned with its back surface contacting the front of the resin layer adjacent the die's front side, and a first solder resist layer is placed with its back surface contacting the front of the passivation layer. The redistribution layer includes first activated portions of the resin layer near the pads, forming electrical connections from the pads to the resin's back surface. Second activated portions extend along the resin's back surface toward the edge sides, while third activated portions run along the resin layer surrounding the die's edge sides. A first interconnect structure extends from the second activated portions, through the passivation and solder resist layers.
METHOD FOR GENERATING AN UPDATE FILE AND CORRESPONDING SERVER DEVICE, UPDATING METHOD AND CORRESPONDING CLIENT DEVICE, UPDATING METHOD AND CORRESPONDING SYSTEM
A server builds an update file to update software. The server compiles source code of an updated version of the software, generating a binary file of the updated version of the software. Memory locations are mapped to sections of the binary file based on mappings of sections of a binary file of a prior version of the software. Bits of sections of a plurality of sections of the binary file of the prior version are logically combined, bit-by-bit, with bits of corresponding sections of the binary file of the updated version. The logically combining includes: applying an exclusive or operation; or applying an exclusive nor operation. The update file is built based on the mapping of the memory locations and on results of the logical combining.
A wafer-level package includes a first integrated circuit die having pads on its front side and a second integrated circuit die having pads on its front side, with a back side of the second die attached to the front side of the first die by an adhesive layer. A resin layer containing an activatable catalyst material is disposed across the front side of the first die, along edge sides of the second die, and across the front side of the second die. Selected portions of the resin layer are activated by laser radiation and metallized to form a redistribution layer providing electrical interconnection between the dies. A solder resist layer is formed over the resin layer, and solder balls are connected to metallized portions of the redistribution layer. The laser-direct-structuring process enables formation of conductive interconnects extending over die edges without conventional drilling or photo-patterning.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
11.
HEMT DEVICE HAVING LOW CONDUCTION LOSSES AND MANUFACTURING PROCESS THEREOF
A manufacturing process forms an HEMT device. For the manufacturing process includes forming, from a wafer of silicon carbide having a surface, an epitaxial layer of silicon carbide on the surface of the wafer A semiconductive heterostructure is formed on the epitaxial layer, and the wafer of silicon carbide is removed.
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
12.
METHOD AND APPARATUS FOR MANAGING WAVEFORM DATA AND DELAYS IN A WAVEFORM GENERATOR
A signal decode circuit is coupled to a buffer for each signal channel. A memory includes a shared area configured to store waveform data sets, each waveform data set including a sequence of coded waveform values specifying waveform step states. The shared area further stores delay data sets, each delay data set including a digital delay value for each signal channel defining a delay profile. A signal pointer addresses the shared area to read one waveform data set from the memory with the sequence of coded waveform values being selectively loaded into one or more of the buffers. A delay pointer addresses the shared area to read one delay data set from the memory with the digital delay values used to control delayed actuation of the signal decode circuits to decode the sequence of coded waveform values from the buffers and generate waveform signals in accordance with the delay profile.
The present disclosure relates to a device comprising a first transistor and a first circuit comprising first and second terminals, the first circuit being configured to generate a first voltage representing the temperature of the first transistor, a first terminal of the first circuit being coupled to the drain of the first transistor.
H03K 17/0812 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit
H03K 17/08 - Modifications for protecting switching circuit against overcurrent or overvoltage
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
14.
Communication method for near-field communication devices
A first near-field communication device is remotely powered by a second near-field communication device. The first near-field communication device receives from the second near-field communication device a frame indicating a failure of a data reception by the second near-field communication device. In response, at least one transmission parameter of the first near-field communication device is modified prior to another attempt of transmission of the data.
H04B 5/77 - Near-field transmission systems, e.g. inductive or capacitive transmission systems specially adapted for specific purposes for interrogation
H04B 5/20 - Near-field transmission systems, e.g. inductive or capacitive transmission systems characterised by the transmission techniqueNear-field transmission systems, e.g. inductive or capacitive transmission systems characterised by the transmission medium
H04L 1/18 - Automatic repetition systems, e.g. Van Duuren systems
An irrigation system includes a fluid-inlet, a first fluid-path coupled to the fluid-inlet and having a first valve for controlling fluid-flow, and a second fluid-path coupled to the fluid-inlet and having a second valve for controlling fluid-flow. Fluid flow through a power harvester coupled to the second fluid-path causes generation of electricity. An energy storage device stores the generated electricity. A sensor measures the energy stored in the energy storage device. A controller is coupled to the sensor, the first valve, and the second valve. The controller determines if the stored energy is below a threshold, to open the second valve to allow fluid-flow through the second fluid-path and activate the power harvester when the stored energy is below the threshold, to close the second valve when the stored energy reaches or exceeds the threshold, and to control the first valve independently of the electricity generation to regulate irrigation.
H02K 7/18 - Structural association of electric generators with mechanical driving motors, e.g.with turbines
H02N 2/18 - Electric machines in general using piezoelectric effect, electrostriction or magnetostriction producing electrical output from mechanical input, e.g. generators
16.
SYSTEM AND METHOD FOR POWER MODULE DEFECT DETECTION
In an embodiment, a method includes: capturing a first image of a power module, the power module including a power electronics circuit, the power electronics circuit including power semiconductor dies; identifying positions of the power semiconductor dies in the first image with a die detection model; extracting second images of the power semiconductor dies from the first image according to the positions of the power semiconductor dies in the first image; and identifying defects of the power semiconductor dies in the second images with a defect detection model, the defect detection model being different from the die detection model.
The present disclosure is directed to semiconductor packages manufactured utilizing a leadframe with varying thicknesses. The leadframe with varying thicknesses has a reduced likelihood of deformation while being handled during the manufacturing of the semiconductor packages as well as when being handled during a shipping process. The method of manufacturing is not required to utilize a leadframe tape based on the leadframe with varying thicknesses. This reduces the overall manufacturing costs of the semiconductor packages due to the reduced materials and steps in manufacturing the semiconductor packages as compared to a method that utilizes a leadframe tape to support a leadframe. The semiconductor packages may include leads of varying thicknesses formed by utilizing the leadframe of varying thicknesses to manufacture the semiconductor packages.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
A pre-molded leadframe includes a laminar structure having empty spaces therein and a first thickness with a die pad having opposed first and second die pad surfaces. Insulating pre-mold material is molded onto the laminar structure. The pre-mold material penetrates the empty spaces and provides a laminar pre-molded substrate having the first thickness with the first die pad surface left exposed. The die pad has a second thickness that is less than the first thickness. One or more pillar formations are provided protruding from the second die pad surface to a height equal to a difference between the first and second thicknesses. With the laminar structure clamped between surfaces of a mold, the first die pad surface and pillar formations abut against the mold surfaces. The die pad is thus effectively clamped between the clamping surfaces countering undesired flashing of the pre-mold material over the first die pad surface.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
A monolithic component includes a field-effect power transistor and at least one first Schottky diode inside and on top of a gallium nitride substrate.
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
H10D 64/00 - Electrodes of devices having potential barriers
The present disclosure relates to a method for manufacturing electronic chips comprising, in order:
The present disclosure relates to a method for manufacturing electronic chips comprising, in order:
a. forming metal contacts on the side of a first face of a semiconductor substrate, in and on which a plurality of integrated circuits have been previously formed;
The present disclosure relates to a method for manufacturing electronic chips comprising, in order:
a. forming metal contacts on the side of a first face of a semiconductor substrate, in and on which a plurality of integrated circuits have been previously formed;
b. depositing a first protective resin on the metal contacts and the first face of the semiconductor substrate;
The present disclosure relates to a method for manufacturing electronic chips comprising, in order:
a. forming metal contacts on the side of a first face of a semiconductor substrate, in and on which a plurality of integrated circuits have been previously formed;
b. depositing a first protective resin on the metal contacts and the first face of the semiconductor substrate;
c. forming first trenches of a first width on the side of a second face of the semiconductor substrate;
The present disclosure relates to a method for manufacturing electronic chips comprising, in order:
a. forming metal contacts on the side of a first face of a semiconductor substrate, in and on which a plurality of integrated circuits have been previously formed;
b. depositing a first protective resin on the metal contacts and the first face of the semiconductor substrate;
c. forming first trenches of a first width on the side of a second face of the semiconductor substrate;
d. depositing a second protective resin in the first trenches and on the second face of the semiconductor substrate;
The present disclosure relates to a method for manufacturing electronic chips comprising, in order:
a. forming metal contacts on the side of a first face of a semiconductor substrate, in and on which a plurality of integrated circuits have been previously formed;
b. depositing a first protective resin on the metal contacts and the first face of the semiconductor substrate;
c. forming first trenches of a first width on the side of a second face of the semiconductor substrate;
d. depositing a second protective resin in the first trenches and on the second face of the semiconductor substrate;
e. forming second trenches of a second width, less than the first width, opposite the first trenches up to the metal contacts; and
The present disclosure relates to a method for manufacturing electronic chips comprising, in order:
a. forming metal contacts on the side of a first face of a semiconductor substrate, in and on which a plurality of integrated circuits have been previously formed;
b. depositing a first protective resin on the metal contacts and the first face of the semiconductor substrate;
c. forming first trenches of a first width on the side of a second face of the semiconductor substrate;
d. depositing a second protective resin in the first trenches and on the second face of the semiconductor substrate;
e. forming second trenches of a second width, less than the first width, opposite the first trenches up to the metal contacts; and
f. forming third trenches opposite the second trenches, the third trenches extending through the metal contacts.
According to an aspect, a method is proposed for defining placements, in a volatile memory, of temporary scratch buffers used during an execution of an artificial neural network, the method comprising: determining an execution order of layers of the neural network, defining placements, in a heap memory zone of the volatile memory, of intermediate result buffers generated by each layer, according to the execution order of the layers, determining at least one free area of the heap memory zone over the execution of the layers, defining placements of temporary scratch buffers in the at least one free area of the heap memory zone according to the execution order of the layers.
A device is configured to receive a first carrier signal, and deliver a second carrier signal, and has a phase-locked loop including a first domain including an oscillator configured to generate a signal at a given frequency, and a circuit configured to generate information representative of the frequency of the signal generated by the oscillator, and to generate the second carrier signal and a clock signal, the first domain being clocked by the first carrier signal, a second domain, clocked by the clock signal, including a circuit configured to compare the frequency of the signal generated by the oscillator with the frequency of the first carrier signal and to control the oscillator, a matching circuit configured to transfer information representative of the frequency of the signal generated by the oscillator from the first domain to the second domain.
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
A capacitive element includes a first conductive layer delimited by an outline and a low voltage dielectric layer covering the first conductive layer. A second conductive layer covers the low voltage dielectric layer and includes: a first portion located over a central zone of the first conductive layer which forms a first capacitor electrode; and a second portion located over the first conductive layer at the inner border of the entire outline of the first conductive layer, and over the front face at the outer border of the entire outline of the first conductive layer. The first portion and the second portion of the second conductive layer are electrically separated by an annular opening extending through the second conductive layer. The first conductive layer is electrically connected to the second portion of the second conductive layer to form a second capacitor electrode.
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
The present disclosure relates to an electronic device comprising a wafer comprising a first upper surface having at least one first contact arranged thereon; and at least one die comprising a second upper surface having at least one second contact arranged thereon, and at least one first lateral surface orthogonal to the second upper surface, said first contact being coupled to said second contact by a connector comprising one first conductive pillar formed on said first contact of said wafer; one second conductive pillar formed on said second contact of said die; and at least one conductive ball positioned in contact with at least a first upper portion of said first pillar(s) and in contact with at least one second upper portion of said second pillar(s).
H05K 3/30 - Assembling printed circuits with electric components, e.g. with resistor
H05K 3/34 - Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
H05K 3/40 - Forming printed elements for providing electric connections to or between printed circuits
25.
METHOD FOR CONTROLLING AN ANALOG-TO-DIGITAL CONVERTER
The present description provides for a method of controlling an analog-to-digital converter. In an example method, the most significant bits are determined by successive approximations. Further, least significant bits are determined by a time-to-digital conversion by applying a first ramp to the output of a first digital-to-analog converter with a third digital-to-analog converter and by applying a second ramp to the output of the second digital-to-analog converter with a fourth digital-to-analog converter. The variation direction of the first and second ramps is determined by the comparison of the outputs of the first digital-to-analog converter and second digital-to-analog converter at the end of the successive approximations.
A trench in a semiconductor substrate is lined with a first insulation layer. A hard mask layer deposited on the first insulation layer is used to control performance of an etch that selectively removes a first portion of the first insulating layer from an upper trench portion while leaving a second portion of first insulating layer in a lower trench portion. After removing the hard mask layer, an upper portion of the trench is lined with a second insulation layer. An opening in the trench that includes a lower open portion delimited by the second portion of first insulating layer in the lower trench portion and an upper open portion delimited by the second insulation layer at the upper trench portion, is then filled by a single deposition of polysilicon material forming a unitary gate/field plate conductor of a field effect rectifier diode.
CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE (France)
STMicroelectronics (Crolles 2) SAS (France)
STMicroelectronics S.r.l. (Italy)
STMicroelectronics (Rousset) SAS (France)
UNIVERSITE D'AIX MARSEILLE (France)
Inventor
Della Marca, Vincenzo
Melul, Franck
La Rosa, Francesco
Niel, Stephan
Regnier, Arnaud
Conte, Antonino
Miridi, Nadia
Abstract
The present disclosure relates to a memory cell (1) and to a method of erasing the memory cell (1). The memory cell comprises a doped well (100) of a first conductivity type and a transistor (T). Transistor (T) comprises a doped first region (106) of a second conductivity type opposite to the first conductivity type, the first doped region extending in the doped well (100); a buried doped channel (118) of the second conductivity type extending in the doped well (100); and a gate stack (108) resting on the doped well (100), above the buried doped channel (118). The gate stack (108) comprises a first layer (110) adapted to trap charges, a second insulating layer (112) resting on the first layer and a third conductive layer (114) resting on the second layer.
An electronic control unit includes a communication circuit designed to receive intelligent transport system (ITS) messages, an authentication circuit for authenticating the received messages, and a secure element containing a hardware-secure non-volatile memory and a continually active clock counter. The secure element is configured to assign a timestamp data item from the clock counter to each of the authenticated received messages and to store the authenticated messages along with their respective timestamp data in the hardware-secure non-volatile memory. The secure element assigns a lifetime to each of the authenticated received ITS messages recorded in the hardware-secure non-volatile memory, and enables direct rejection of a received ITS message that repeats a previously received, authenticated, and recorded ITS message whose lifetime has not expired.
A substrate made of doped single-crystal silicon has an upper surface. A doped single-crystal silicon layer is formed by epitaxy on top of and in contact with the upper surface of the substrate. Either before or after forming the doped single-crystal silicon layer, and before any other thermal treatment step at a temperature in the range from 600° C. to 900° C., a denuding thermal treatment is applied to the substrate for several hours. This denuding thermal treatment is at a temperature higher than or equal to 1,000° C.
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
H01L 21/763 - Polycrystalline semiconductor regions
H10D 84/40 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or with at least one component covered by groups or , e.g. integration of IGFETs with BJTs
30.
POWER SEMICONDUCTOR DEVICE WITH A DOUBLE ISLAND SURFACE MOUNT PACKAGE
A power semiconductor device including a first and second die, each including a plurality of conductive contact regions and a passivation region including a number of projecting dielectric regions and a number of windows. Adjacent windows are separated by a corresponding projecting dielectric region with each conductive contact region arranged within a corresponding window. A package of the surface mount type houses the first and second dice. The package includes a first bottom insulation multilayer and a second bottom insulation multilayer carrying, respectively, the first and second dice. A covering metal layer is arranged on top of the first and second dice and includes projecting metal regions extending into the windows to couple electrically with corresponding conductive contact regions. The covering metal layer moreover forms a number of cavities, which are interposed between the projecting metal regions so as to overlie corresponding projecting dielectric regions.
Merged-PiN-Schottky, MPS, device comprising: a solid body having a first electrical conductivity; an implanted region extending into the solid body facing a front side of the solid body, having a second electrical conductivity opposite to the first electrical conductivity; and a semiconductor layer extending on the front side, of a material which is a transition metal dichalcogenide, TMD. A first region of the semiconductor layer has the second electrical conductivity and extends in electrical contact with the implanted region, and a second region of the semiconductor layer has the first electrical conductivity and extends adjacent to the first region and in electrical contact with a respective surface portion of the front side having the first electrical conductivity.
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
H10D 64/62 - Electrodes ohmically coupled to a semiconductor
The present disclosure relates to an NFC device configured for wireless power transfer, the NFC device comprising an antenna, a frontend circuit coupled to the antenna, a microcontroller coupled to the frontend circuit, the microcontroller comprising an analog-to-digital converter. The analog-to-digital converter is configured to receive an analog amplitude and/or phase signal from the frontend circuit, and to convert the analog signal into a digital signal. The microcontroller is configured to process the digital signal in order to detect a variation in the amplitude and/or phase of the analog signal, so as to detect a change of impedance within the field of the NFC device.
H02J 50/60 - Circuit arrangements or systems for wireless supply or distribution of electric power responsive to the presence of foreign objects, e.g. detection of living beings
H02J 50/20 - Circuit arrangements or systems for wireless supply or distribution of electric power using microwaves or radio frequency waves
H02J 50/80 - Circuit arrangements or systems for wireless supply or distribution of electric power involving the exchange of data, concerning supply or distribution of electric power, between transmitting devices and receiving devices
In an embodiment a switch includes a first MOS transistor having its source connected to its channel-forming region and coupled with a first terminal of the switch, its drain coupled with a second terminal of the switch, and its gate connected to a first node of the switch, a diode coupling the first terminal with the first node, a capacitive element coupling a third terminal of the switch with the first node, the third terminal being configured to receive a control signal for the switch and a discharge circuit coupling the first node with the first terminal, the discharge circuit configured to conduct only when a voltage between the first node and the first terminal is greater than or equal to a threshold.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H03K 17/10 - Modifications for increasing the maximum permissible switched voltage
H03K 17/22 - Modifications for ensuring a predetermined initial state when the supply voltage has been applied
34.
System and method for attaching an integrated circuit card to a communication network
In accordance with an embodiment, a method includes: receiving a notification of a network loss from a mobile communication network, the notification comprising a current network loss cause; selecting a network loss event duration estimate among a plurality of network loss event duration estimates stored on an integrated circuit card and indexed according to a corresponding plurality of network loss cause indices; selecting a stored profile of a plurality of stored profiles on the integrated circuit card based on the selected network loss event duration estimate, wherein the plurality of stored profiles are associated with user subscriptions; and attaching to the mobile communication network using the selected stored profile when the selected stored profile is not already enabled.
An electronic circuit includes an upper substrate and a lower substrate. An electronic integrated circuit chip is positioned between the upper and lower substrates. The chip includes contact elements coupled to the upper substrate. A first region made of a first material is arranged between the chip and a heat transfer area crossing the lower substrate. A second region filled with a second material couples the lower and upper substrates and laterally surrounds the first region. The first material has a thermal conductivity greater than a thermal conductivity of the second material.
A thermographic sensor is proposed. The thermographic sensor includes one or more thermo-couples, each for providing a sensing voltage depending on a difference between a temperature of a hot joint and a temperature of a cold joint of the thermo-couple; the thermographic sensor further comprises one or more sensing transistors, each driven according to the sensing voltages of one or more corresponding thermo-couples for providing a sensing electrical signal depending on its temperature and on the corresponding sensing voltages. A thermographic device including the thermographic sensor and a corresponding signal processing circuit, and a system including one or more thermographic devices are also proposed.
An embodiment buck converter control circuit comprises an error amplifier configured to generate an error signal based on a feedback signal and a reference signal, a pulse generator circuit configured to generate a pulsed signal having switching cycles set to high and low as a function of the error signal, a driver circuit configured to generate a drive signal for an electronic switch of the buck converter as a function of the pulsed signal, a variable load, connected between two output terminals of the buck converter, configured to absorb a current based on a control signal, and a detector circuit configured to monitor a first signal indicative of an output current provided by the buck converter and a second signal indicative of a negative transient of the output current, and verify whether the second signal indicates a negative transient of the output current.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 3/156 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
38.
METHOD OF OPERATING BATTERY MANAGEMENT SYSTEMS, CORRESPONDING DEVICE AND VEHICLE
A method can be used to control a battery management system. A first voltage drop is sensed between a first terminal of a first battery cell and a second terminal of the first battery cell and a second voltage drop is sensed between a first terminal of a second battery cell and a second terminal of the second battery cell. A faulty condition is detected in the first battery cell or the second battery cell based on the first voltage drop or the second voltage drop. The first voltage drop is swapped for a first swapped voltage drop between a common terminal and the second terminal of the second battery cell.
G01R 31/396 - Acquisition or processing of data for testing or for monitoring individual cells or groups of cells within a battery
B60K 6/28 - Arrangement or mounting of plural diverse prime-movers for mutual or common propulsion, e.g. hybrid propulsion systems comprising electric motors and internal combustion engines the prime-movers consisting of electric motors and internal combustion engines, e.g. HEVs characterised by apparatus, components or means specially adapted for HEVs characterised by the electric energy storing means, e.g. batteries or capacitors
B60L 3/00 - Electric devices on electrically-propelled vehicles for safety purposesMonitoring operating variables, e.g. speed, deceleration or energy consumption
B60L 50/60 - Electric propulsion with power supplied within the vehicle using propulsion power supplied by batteries or fuel cells using power supplied by batteries
B60L 58/20 - Methods or circuit arrangements for monitoring or controlling batteries or fuel cells, specially adapted for electric vehicles for monitoring or controlling batteries of two or more battery modules having different nominal voltages
H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
An electronic cell includes an integrated stack of structures including, successively: a first electrode; an ovonic threshold switch layer below the first electrode; and a fixed resistor below the ovonic threshold switch layer. A second electrode may be included between fixed resistor and the ovonic threshold switch layer. A memory layer, for example a phase change material layer, a resistive random-access memory layer or a magneto-resistive random-access memory layer, may be included between the first electrode and the ovonic threshold switch layer.
A MEMS pressure sensor packaged with a molding compound. The MEMS pressure sensor features a lead frame, a MEMS semiconductor die, a second semiconductor die, multiple pluralities of bonding wires, and a molding compound. The MEMS semiconductor die has an internal chamber, a sensing component, and apertures. The MEMS semiconductor die and the apertures are exposed to an ambient atmosphere. A method is desired to form a MEMS pressure sensor package that reduces defects caused by mold flashing and die cracking. Fabrication of the MEMS pressure sensor package comprises placing a lead frame on a lead frame tape; placing a MEMS semiconductor die adjacent to the lead frame and on the lead frame tape with the apertures facing the tape and being sealed thereby; attaching a second semiconductor die to the MEMS semiconductor die; attaching pluralities of bonding wires to form electrical connections between the MEMS semiconductor die, the second semiconductor die, and the lead frame; and forming a molding compound.
In accordance with an embodiment, a hard disk drive includes voice coil motors (VCMs) coupled to respective control units configured to drive retract an operation of the VCMs in the hard disk drive. The retract operation of the VCMs includes a sequence of retract steps. The control units are allotted respective time slots for communication over a communication line with the respective time slots synchronized via the common clock line, and are configured to drive sequences of retract steps of the VCMs in the hard disk drive in a timed relationship.
An embedded electronic system includes a volatile memory and a processor configured to execute a low-level operating system that manages allocation of areas of the volatile memory to a plurality of high-level operating systems. Each high-level operating system executes one or more applications. The system is configured so that execution data of one or a plurality of tasks of a first application are partly transferred, by the low-level operating system, from the volatile memory to a non-volatile memory when the execution of the task of the first application is interrupted by the execution of a task of a second application. The system is also configured so that the applications of any one of the high-level operating systems do not have access to the areas of the volatile memory allocated to the applications of all the other high-level operating systems.
G06F 21/53 - Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity, buffer overflow or preventing unwanted data erasure by executing in a restricted environment, e.g. sandbox or secure virtual machine
G06F 12/0842 - Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
G06F 12/14 - Protection against unauthorised use of memory
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
43.
CONTROL DEVICE FOR A SWITCHING VOLTAGE REGULATOR HAVING IMPROVED CONTROL PERFORMANCE AND CONTROL METHOD
Provided is a control device is for a switching voltage regulator having a switching circuit. The control device receives input and output voltages of the switching circuit and a measurement signal indicative of a current of the switching circuit. The control device has: a feedback module that detects an error signal indicative of a difference between the output voltage and a nominal voltage, and provides a control signal as a function of the error signal; a threshold-correction module that provides offset and ramp signals; and a driving-signal generation module coupled to the feedback and threshold-correction modules, which receives the measurement signal, compares the measurement signal with a threshold and, in response, provides a modulated signal for driving the switching circuit. The threshold is a function of the control, offset and ramp signals. The threshold-correction module provides the offset signal as a function of the input or output voltages.
According to an embodiment, a circuit includes a core and low-frequency recovery circuits. The core circuit is configured to bias a resistive sensor used to measure a fly height of a hard disk drive. The core circuit is additionally configured to amplify a high-frequency component of a sensing signal of the resistive sensor, the sensing signal indicating the fly height. The low-frequency recovery circuit is configured to amplify the sensing signal's low-frequency component.
G01B 7/14 - Measuring arrangements characterised by the use of electric or magnetic techniques for measuring distance or clearance between spaced objects or spaced apertures
G11B 27/36 - Monitoring, i.e. supervising the progress of recording or reproducing
H03F 3/16 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only with field-effect devices
45.
ELECTRONIC MODULE FOR GENERATING LIGHT PULSES FOR LIDAR APPLICATIONS AND METHOD FOR MANUFACTURING THE ELECTRONIC MODULE
An electronic module for generating light pulses includes an electronic card or interposer, a LASER-diode lighting module, and a LASER-diode driver module. The interposer has an edge recess in which the lighting module is completely inserted. The driver module is arranged on top of the interposer and the lighting module. The electrical connections for driving the LASER diodes are obtained without resorting to wire bonding in order to reduce the parasitic inductances.
H01S 5/062 - Arrangements for controlling the laser output parameters, e.g. by operating on the active medium by varying the potential of the electrodes
H01S 5/0683 - Stabilisation of laser output parameters by monitoring the optical output parameters
H01S 5/40 - Arrangement of two or more semiconductor lasers, not provided for in groups
46.
CONTROL CIRCUIT FOR A SWITCHING STAGE OF AN ELECTRONIC CONVERTER AND CORRESPONDING CONVERTER DEVICE
A control circuit for a switching stage of an electronic converter includes a PWM signal generator that generates a PWM signal to drive the switching stage of the electronic converter. A loop comparator circuit receives the regulated output voltage of the electronic converter and receives a sum signal from an adder circuit. The loop comparator circuit generates a comparison signal having a first or second logic value in response to the regulated output voltage reaching the sum signal or failing to reach the sum signal. The adder circuit generates the sum signal as a sum of a reference voltage and a programmable offset voltage that is generated by a programmable voltage generator based on a digital word signal. A feedback circuit is coupled to the loop comparator circuit and the PWM signal generator, and provides the digital word signal to the programmable voltage generator.
H02M 3/157 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
A microelectromechanical gyroscope is provided with a detection structure having: a substrate with a top surface parallel to a horizontal plane (xy); a mobile mass, suspended above the substrate to perform, as a function of a first angular velocity (Ωx) around a first axis (x) of the horizontal plane (xy), at least a first detection movement of rotation around a second axis (y) of the horizontal plane; and a first and a second stator elements integral with the substrate and arranged underneath the mobile mass to define a capacitive coupling, a capacitance value thereof is indicative of the first angular velocity (Ωx). The detection structure has a single mechanical anchorage structure for anchoring both the mobile mass and the stator elements to the substrate, arranged internally with respect to the mobile mass, which is coupled to this single mechanical anchorage structure by coupling elastic elements yielding to torsion around the second axis; the stator elements are integrally coupled to the single mechanical anchorage structure in an arrangement suspended above the top surface of the substrate.
G01C 19/5712 - Turn-sensitive devices using vibrating masses, e.g. vibratory angular rate sensors based on Coriolis forces using masses driven in reciprocating rotary motion about an axis the devices involving a micromechanical structure
48.
CONNECTING STRIP FOR DISCRETE AND POWER ELECTRONIC DEVICES
A connecting strip of conductive elastic material having an arched shape having a concave side and a convex side. The connecting strip is fixed at the ends to a support carrying a die with the convex side facing the support. During bonding, the connecting strip undergoes elastic deformation and presses against the die, thus electrically connecting the at least one die to the support.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
49.
CONTROLLER WITH PROTECTION AGAINST CROSS-CONDUCTION FOR AN ELECTRONIC CIRCUIT INCLUDING A PAIR OF SWITCHES AND RELATED CONTROL METHOD
A controller for an electronic circuit that includes a first and a second switch is provided. The controller includes an event detector stage that receives logic electrical signals and a pulse generator circuit, which is coupled to the event detector stage and generates a dead time signal based on edges of the logic electrical signals detected by the event detector stage. The dead time signal includes pulses delimited by an edge of a first type and by a subsequent edge of a second type. A combinatorial sampling circuit generates a first and a second sampled preliminary signal. An update stage updates the values of the first and the second control signals at each pulse of the dead time signal based on the first and the second sampled preliminary signals, subsequently to the edge of the first type or the second type of the pulse of the dead time signal.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
The present disclosure is directed to semiconductor packages that include a molding compound having at least one raised portion that extends outward from the package. In some embodiments, the semiconductor packages have a plurality of raised portions, and a plurality of conductive layers are on the plurality of raised portions. The plurality of raised portions and the plurality of conductive layers are utilized to mount the semiconductor packages to an external electronic device (e.g., a printed circuit board (PCB), another semiconductor package, an external electrical connection, etc.). In some embodiments, the semiconductor packages have a single raised portion with a plurality of conductive layers that are on the single raised portion. The single raised portion and the plurality of conductive layers are utilized to mount the semiconductor packages to the external electronic device. The plurality of conductive layers on the plurality of raised portions or the single raised portion may be formed by a laser direct structuring (LDS) process.
The packaged power electronic device has a bearing structure including a base section and a transverse section extending transversely to the base section. A die is bonded to the base section of the bearing structure and has a first terminal on a first main face and a second and a third terminal on a second main face. A package of insulating material embeds the semiconductor die, the second terminal, the third terminal and at least partially the carrying base. A first, a second and a third outer connection region are electrically coupled to the first, the second and the third terminals of the die, respectively, are laterally surrounded by the package and face the second main surface of the package. The transverse section of the bearing structure extends from the base section towards the second main surface of the package and has a higher height with respect to the die.
The present disclosure is directed to a light-signal communication receiver device including a photo-receiving diode configured to generate a current signal on a first node from a received light signal, a preamplifier configured to convert the current signal on the first node into a voltage signal on a second node, and a differential amplifier including a first input connected to the first node and a second input connected to a third node coupled to the second node via an adjustment circuit. The adjustment circuit is configured to offset the level of the voltage signal of the second node, on the third node, in a controlled manner by a control signal.
A sensor device includes a passive infrared sensor, a control circuit, and a lens that directs infrared radiation onto the passive infrared sensor. The lens includes an obstruction that asymmetrically blocks transmission of infrared radiation through the lens. The control circuit is configured to determine the direction of crossing of individuals passing in front of the sensor device based on sensor signals from the passive infrared sensor.
G08B 13/193 - Actuation by interference with heat, light, or radiation of shorter wavelengthActuation by intruding sources of heat, light, or radiation of shorter wavelength using passive radiation detection systems using infrared-radiation detection systems using focusing means
G01J 5/05 - Means for preventing contamination of the components of the optical systemMeans for preventing obstruction of the radiation path
G01J 5/068 - Arrangements for eliminating effects of disturbing radiationArrangements for compensating changes in sensitivity by controlling parameters other than temperature
G01J 5/0806 - Focusing or collimating elements, e.g. lenses or concave mirrors
G08B 13/19 - Actuation by interference with heat, light, or radiation of shorter wavelengthActuation by intruding sources of heat, light, or radiation of shorter wavelength using passive radiation detection systems using infrared-radiation detection systems
In an embodiment an electronic device includes a first electronic circuit having a capacitive element with a variable capacitance, wherein the first electronic circuit is configured to couple the capacitive element to an antenna, to measure, by successive iterations, a first analog signal representative of a variation of an instantaneous electric power received by the antenna or representative of the instantaneous electric power received by the antenna and to modify the capacitance of the capacitive element until an amplitude of the instantaneous electric power received by the antenna is a maximum, wherein the antenna is configured to capture an amplitude-modulated electromagnetic field.
A method includes receiving a histogram output from a detector sensor, and calculating a median point of a pulse waveform within the histogram. The pulse waveform has an even probability distribution over at least one quantization step of the histogram around the median point. A corresponding apparatus can include a detector sensor and a co-processor coupled to the detector sensor.
The present disclosure is directed to a package that includes a transparent layer that is on and covers a sensor of a die as well as a plurality of electrical connections that extend from a first surface of the package to the second surface of the package opposite to the first surface. In at least one embodiment of a package, the electrical connections each include a conductive structure that extends through the transparent layer to a first side of a corresponding contact pad of the die, and at least one electrical that extends into the second surface of the die to a second side of the corresponding contact pad that is opposite to the first side. In at least another embodiment of a package, the electrical connections include a conductive structure that extends through a molding compound to a first side of a corresponding contact pad of the die, and at least one electrical via that extends into the second surface of the die to a second side of the corresponding contact pad opposite to the first side.
H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
First and second wells are formed in a semiconductor substrate. First and second trenches in the first second wells, respectively, each extend vertically and include a central conductor insulated by a first insulating layer. A second insulating layer is formed on a top surface of the semiconductor substrate. The second insulating layer is selectively thinned over the second trench. A polysilicon layer is deposited on the second insulating layer and then lithographically patterned to form: a first polysilicon portion over the first well that is electrically connected to the central conductor of the first trench to form a first capacitor plate, a second capacitor plate formed by the first well; and a second polysilicon portion over the second well forming a floating gate electrode of a floating gate transistor of a memory cell having an access transistor whose control gate is formed by the central conductor of the second trench.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
Methods and structures for forming highly-doped, ultrathin layers for transistors formed in semiconductor-on-insulator substrates are described. High dopant concentrations may be achieved in ultrathin semiconductor layers to improve device characteristics. Ion implantation at elevated temperatures may mitigate defect formation for stoichiometric dopant concentrations up to about 30%. In-plane stressors may be formed adjacent to channels of transistors formed in ultrathin semiconductor layers.
H10D 30/69 - IGFETs having charge trapping gate insulators, e.g. MNOS transistors
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
H01L 21/70 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereofManufacture of integrated circuit devices or of specific parts thereof
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
H10D 86/00 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
In an embodiment, a radio frequency (RF) receiver circuit includes a main circuit and a wake-up circuit. The main circuit is configured to process RF signals. The wake-up circuit is configured to detect a reception of the RF signals. The wake-up circuit includes an automatic gain control (AGC) loop, and is configured to have a first operating mode where a set point voltage of the loop has a first substantially constant value, and a second operating mode where the set point voltage of the loop has a second value dependent on a power supply voltage of the wake-up circuit.
A wafer level chip scale package (WLCSP) with portions that have different thicknesses. A first passive surface of a die in the WLSCP includes a plurality of surfaces. The plurality of surfaces may include inclined surfaces or flat surfaces. Thicker portions of die, with more semiconductor material remaining are non-critical portions that increase a WLCSP's strength for further processing and handling after formation, and the thinner portions are critical portions that reduce a Coefficient of Thermal Expansion (CTE) mismatch between a WLCSP and a PCB.
A rectifying bridge includes a bypass circuit with a resistor and a thyristor connected in parallel between a second internal node and a second output node. The bypass circuit limits inrush current during charging of a capacitor connected between the first and second output nodes and switches the thyristor to an “on” state after the capacitor reaches a predetermined charge level to prevent overheating of the resistor. The rectifying bridge further includes first and second branches connected in parallel between a first internal node and the second internal node, each branch including a pair of diodes configured to rectify an input AC voltage. A control device, having a triac and a diode series-connected between the triac and the thyristor, delivers a control signal to the thyristor to enable switching. The control device operates independently of input voltage polarity and can be implemented as part of an integrated circuit.
In a multi-level hybrid DC-DC converter with a flying capacitor, a feedback circuit includes a first oscillator and produces a first clock signal with a frequency dependent on an output voltage. A second oscillator produces a second clock signal having a frequency dependent on a reference voltage. A logic circuit switches, as a function of the first and second clock signals, connection of the flying capacitor between one state where the flying capacitor is connected between an input node and a switching node, and another state where the capacitor is connected between the switching node and a ground node. The duty cycle of the first/second clock signal varies so that when the flying capacitor voltage is lower than a target voltage a duration of the one state is increased, and when the flying capacitor voltage is higher than the target voltage a duration of the another state is increased.
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
A device for monitoring the health state is made in a chip including a semiconductor die integrating an electric potential sensor and a cardiac parameter determination unit. The potential sensor is configured to detect potential variations on the body of a living being and associated with a heart rhythm and to generate a cardiac signal. The cardiac parameter determination unit is configured to receive the cardiac signal and determine cardiac parameters indicative of a health state. In particular, the cardiac parameter determination unit is configured to detect triggering events and to determine features of the cardiac signal in time windows defined by the triggering events. The die also integrates a decision unit, configured to receive the cardiac parameters and generate a health signal based on a comparison with threshold values. The cardiac parameters include heart rate and QRS-complex.
A control module is used to control a switching buck-boost converter that includes an inductor, a capacitor, a first top switch and a second top switch, a first bottom switch and a second bottom switch and a diode coupled to the second top switch. The control module controls the switching buck-boost converter so as to alternate: first time periods, in which the second top switch is open and cycles of charge and discharge of the inductor are carried out, during which the inductor is traversed by a current that also passes through the diode and charges the capacitor; and second time periods, in which the first and second top switches are open and the first and second bottom switches are closed so that the current in the inductor recirculates, and the capacitor is discharged by a current that flows in the load.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
65.
4H-SIC ELECTRONIC DEVICE WITH IMPROVED SHORT-CIRCUIT PERFORMANCES, AND MANUFACTURING METHOD THEREOF
An electronic device includes a semiconductor body of silicon carbide, and a body region at a first surface of the semiconductor body. A source region is disposed in the body region. A drain region is disposed at a second surface of the semiconductor body. A doped region extends seamlessly at the entire first surface of the semiconductor body and includes one or more first sub-regions having a first doping concentration and one or more second sub-regions having a second doping concentration lower than the first doping concentration. Thus, the device has zones alternated to each other having different conduction threshold voltage and different saturation current.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
66.
HEMT TRANSISTOR OF THE NORMALLY OFF TYPE INCLUDING A TRENCH CONTAINING A GATE REGION AND FORMING AT LEAST ONE STEP, AND CORRESPONDING MANUFACTURING METHOD
A method forms an HEMT transistor of the normally off type, including: a semiconductor heterostructure, which comprises at least one first layer and one second layer, the second layer being set on top of the first layer; a trench, which extends through the second layer and a portion of the first layer; a gate region of conductive material, which extends in the trench; and a dielectric region, which extends in the trench, coats the gate region, and contacts the semiconductor heterostructure. A part of the trench is delimited laterally by a lateral structure that forms at least one first step. The semiconductor heterostructure forms a first edge and a second edge of the first step, the first edge being formed by the first layer.
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H10D 62/824 - Heterojunctions comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
67.
NORMALLY-OFF TRANSISTOR WITH REDUCED ON-STATE RESISTANCE AND MANUFACTURING METHOD
A normally-off electronic device, comprising: a semiconductor body including a heterostructure that extends over a buffer layer; a recessed-gate electrode, extending in a direction orthogonal to the plane; a first working electrode and a second working electrode at respective sides of the gate electrode; and an active area housing, in the on state, a conductive path for a flow of electric current between the first and second working electrodes. A resistive region extends at least in part in the active area that is in the buffer layer and is designed to inhibit the flow of current between the first and second working electrodes when the device is in the off state. The gate electrode extends in the semiconductor body to a depth at least equal to the maximum depth reached by the resistive region.
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H10D 62/17 - Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
H10D 62/824 - Heterojunctions comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
H10D 64/23 - Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
At start-up of a microelectromechanical system (MEMS) gyroscope, the drive signal is inhibited, and the phase, frequency and amplitude of any residual mechanical oscillation is sensed and processed to determine a process path for start-up. In the event that the sensed frequency of the residual mechanical oscillation is a spurious mode frequency and a quality factor of the residual mechanical oscillation is sufficient, an anti-phase signal is applied as the MEMS gyroscope drive signal in order to implement an active dampening of the residual mechanical oscillation. A kicking phase can then be performed to initiate oscillation. Also, in the event that the sensed frequency of the residual mechanical oscillation is a resonant mode frequency with sufficient drive energy, a quadrature phase signal with phase lock loop frequency control and amplitude controlled by the drive energy is applied as the MEMS gyroscope drive signal in order to induce controlled oscillation.
G01C 19/5762 - Structural details or topology the devices having a single sensing mass the sensing mass being connected to a driving mass, e.g. driving frames
69.
CIRCUITS AND METHODS FOR DEBOUNCING SIGNALS PRODUCED BY A ROTARY ENCODER
A first input node receives a first input signal and a second input node receives a second input signal. The first and second input signals are in phase quadrature. An edge detector circuit senses the first input signal and produces a pulsed signal indicative of edges detected in the first input signal. A pulse skip and reset circuit senses the pulsed signal and the second input signal, and produces a reset signal indicative of pulses detected in the pulsed signal while the second input signal is de-asserted. A sampling circuit senses the second input signal and the reset signal, and produces an output signal that is deasserted in response to assertion of the second input signal and is asserted in response to a pulse being detected in the reset signal.
H03K 5/1254 - Suppression or limitation of noise or interference specially adapted for pulses generated by closure of switches, i.e. anti-bouncing devices
G01D 5/347 - Mechanical means for transferring the output of a sensing memberMeans for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for convertingTransducers not specially adapted for a specific variable using optical means, i.e. using infrared, visible or ultraviolet light with attenuation or whole or partial obturation of beams of light the beams of light being detected by photocells using displacement encoding scales
H03K 3/013 - Modifications of generator to prevent operation by noise or interference
70.
BUCK-BOOST DC-DC CONVERTER CIRCUIT AND CORRESPONDING METHOD OF OPERATION
A buck-boost converter circuit includes a mode selection circuit that asserts a buck enable signal if an input voltage is higher than a lower threshold, and asserts a boost enable signal if the input voltage is lower than an upper threshold. A control circuit asserts a buck PWM signal upon a pulse in a buck clock and de-asserts the buck PWM signal if a buck ramp is higher than a buck control signal, and it keeps the buck PWM signal asserted if the buck enable signal is de-asserted. The control circuit asserts a boost PWM signal upon a pulse in a boost clock and de-asserts the boost PWM signal if a boost ramp is higher than a boost control signal, and it keeps the boost PWM signal de-asserted if the boost enable signal is de-asserted.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 3/157 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
71.
INTEGRATED CIRCUIT COMPRISING AT LEAST ONE BIPOLAR TRANSISTOR AND A CORRESPONDING METHOD OF PRODUCTION
A bipolar transistor includes a common collector region comprising a buried semiconductor layer and an annular well. A well region is surrounded by the annular well and delimited by the buried semiconductor layer. A first base region and a second base region are formed by the well region and separated from each other by a vertical gate structure. A first emitter region is implanted in the first base region, and a second emitter region is implanted in the second base region. A conductor track electrically couples the first emitter region and the second base region to configure the bipolar transistor as a Darlington-type device. Structures of the bipolar transistor may be fabricated in a co-integration with a non-volatile memory cell.
In an embodiment, a method for operating a plurality of delay units include supplying to a first delay unit in a chain an input signal that propagates along delay units in the chain, generating a clock signal as a logic combination of signals input to and output from delay units in the chain and forwarding a feedback signal to the first delay unit in the chain via a first feedback signal path from a last delay unit in the chain to the first delay unit in the chain and a second feedback signal path from an intermediate delay unit in the chain to the first delay unit in the chain, the intermediate delay unit being arranged between the first delay unit and the last delay unit.
H03K 5/14 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of delay lines
H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
The control circuit for a MEMS gyroscope is configured to receive a measurement signal which has a quadrature component and a sensing component. The control circuit has: an input stage which acquires an input signal, generating an acquisition signal, where the input signal is a function of the measurement signal and of a quadrature cancellation signal; a processing stage which extracts a first component of the acquisition signal, indicative of the sensing component of the measurement signal and having a sensing frequency band; and a quadrature correction stage which extracts a second component of the acquisition signal, indicative of the quadrature component of the measurement signal, and generates the quadrature cancellation signal from a reference signal. The quadrature cancellation signal is a signal modulated as a function of the second component of the acquisition signal, at an update frequency which is outside the sensing frequency band.
G01C 19/5712 - Turn-sensitive devices using vibrating masses, e.g. vibratory angular rate sensors based on Coriolis forces using masses driven in reciprocating rotary motion about an axis the devices involving a micromechanical structure
G01C 19/5776 - Signal processing not specific to any of the devices covered by groups
H03M 3/00 - Conversion of analogue values to or from differential modulation
74.
HETEROSTRUCTURE OPTOELECTRONIC DEVICE FOR EMITTING AND DETECTING ELECTROMAGNETIC RADIATION, AND MANUFACTURING PROCESS THEREOF
An optoelectronic device with a semiconductor body that includes: a bottom cathode structure, formed by a bottom semiconductor material, and having a first type of conductivity; and a buffer region, arranged on the bottom cathode structure and formed by a buffer semiconductor material different from the bottom semiconductor material. The optoelectronic device further includes: a receiver comprising a receiver anode region, which is formed by the bottom semiconductor material, has a second type of conductivity, and extends in the bottom cathode structure; and an emitter, which is arranged on the buffer region and includes a semiconductor junction formed at least in part by a top semiconductor material, different from the bottom semiconductor material.
H10F 55/00 - Radiation-sensitive semiconductor devices covered by groups , or being structurally associated with electric light sources and electrically or optically coupled thereto
H10F 30/225 - Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation the devices having only one potential barrier, e.g. photodiodes the potential barrier working in avalanche mode, e.g. avalanche photodiodes
H10F 71/00 - Manufacture or treatment of devices covered by this subclass
H10H 20/812 - Bodies having quantum effect structures or superlattices, e.g. tunnel junctions within the light-emitting regions, e.g. having quantum confinement structures
H10H 20/815 - Bodies having stress relaxation structures, e.g. buffer layers
H10H 20/825 - Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP containing nitrogen, e.g. GaN
H10H 20/826 - Materials of the light-emitting regions comprising only Group IV materials
Merged-PiN-Schottky, MPS, device comprising: a substrate of SiC with a first conductivity; a drift layer of SiC with the first conductivity, on the substrate; an implanted region with a second conductivity, extending at a top surface of the drift layer to form a junction-barrier, JB, diode with the substrate; and a first electrical terminal in ohmic contact with the implanted region and in direct contact with the top surface to form a Schottky diode with the drift layer. The JB diode and the Schottky diode are alternated to each other along an axis: the JB diode has a minimum width parallel to the axis with a first value, and the Schottky diode has a maximum width parallel to the axis with a second value smaller than, or equal to, the first value. A breakdown voltage of the MPS device is greater than, or equal to, 115% of a maximum working voltage of the MPS device in an inhibition state.
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
A MOS transistor, in particular a vertical channel transistor, includes a semiconductor body housing a body region, a source region, a drain electrode and gate electrodes. The gate electrodes extend in corresponding recesses which are symmetrical with respect to an axis of symmetry of the semiconductor body. The transistor also has spacers which are also symmetrical with respect to the axis of symmetry. A source electrode extends in electrical contact with the source region at a surface portion of the semiconductor body surrounded by the spacers and is in particular adjacent to the spacers. During manufacture the spacers are used to form in an auto-aligning way the source electrode which is symmetrical with respect to the axis of symmetry and equidistant from the gate electrodes.
The vertical-conduction electronic power device is formed by a body of wide band gap semiconductor which has a first conductivity type and has a surface, and is formed by a drift region and by a plurality of surface portions delimited by the surface. The electronic device is further formed by a plurality of first implanted regions having a second conductivity type, which extend into the drift region from the surface, and by a plurality of metal portions, which are arranged on the surface. Each metal portion is in Schottky contact with a respective surface portion of the plurality of surface portions so as to form a plurality of Schottky diodes formed by first Schottky diodes and second Schottky diodes, wherein the first Schottky diodes have, at equilibrium, a Schottky barrier having a height different from that of the second Schottky diodes.
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
A system to sanitize a surface includes an emitter. The emitter of the system to sanitize the surface includes: a light source configured to generate light at a sanitizing wavelength; a receiver configured to receive a wireless signal; and a processing circuit for the emitter configured to turn the light source on, turn the light source off, and adjust an intensity of light generated by the light source depending on the wireless signal. The system to sanitize the surface further includes a sensor. The sensor of the system to sanitize the surface includes: a photoelectric transducer configured to convert light at the sanitizing wavelength to a current; and a processing circuit for the sensor powered by the current and in communication with a transmitter to transmit the wireless signal, the processing circuit for the sensor being configured to control emission of the wireless signal depending on a power level supplied by the current.
G08B 7/06 - Signalling systems according to more than one of groups Personal calling systems according to more than one of groups using electric transmission
G08C 17/02 - Arrangements for transmitting signals characterised by the use of a wireless electrical link using a radio link
79.
PACKAGED POWER ELECTRONIC DEVICE, IN PARTICULAR BRIDGE CIRCUIT COMPRISING POWER TRANSISTORS, AND ASSEMBLING PROCESS THEREOF
The device has a first support element forming a first thermal dissipation surface and carrying a first power component; a second support element forming a second thermal dissipation surface and carrying a second power component, a first contacting element superimposed to the first power component; a second contacting element superimposed to the second power component; a plurality of leads electrically coupled with the power components through the first and/or the second support elements; and a thermally conductive body arranged between the first and the second contacting elements. The first and the second support elements and the first and the second contacting elements are formed by electrically insulating and thermally conductive multilayers.
H05K 7/20 - Modifications to facilitate cooling, ventilating, or heating
H01L 23/373 - Cooling facilitated by selection of materials for the device
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
A band-gap circuit for generating a bandgap reference signal includes a first bipolar transistor and a second bipolar transistor of a same type among PNP and NPN types. The first and second bipolar transistors are configured to generate a current varying proportionally with the temperature. A capacitor is connected between a base and an emitter of one or both of the first and second bipolar transistors.
A power MOSFET device includes an active area accommodating a first body region and a second body region having a first and, respectively, a second conductivity value. The second value is higher than the first value. A first channel region is disposed in the first body region between a first source region and a drain region, and the first channel region has and having a first channel length. A second channel region is disposed in the second body region between a second source region and the drain region, and the second channel region has and having a second channel length smaller than the first channel length. A first device portion, having a first threshold voltage, includes the first channel region, and a second device portion, having a second threshold voltage higher than the first threshold voltage, includes the second channel region.
A support substrate supports an electronic chip. An encapsulation coating on the support substrate coats the electronic chip. The encapsulation coating includes a trench surrounding the electronic chip. A heat sink is mounted to the encapsulation coating above the electronic chip. The heat sink is fixed to the encapsulation coating by an adhesive material and a thermal interface material layer is present between the electronic chip and the heat sink. The trench is positioned between the thermal interface material layer and the adhesive material.
A voltage conversion system provides gain and offset trimming for generating a controlled output voltage. The system includes a digital-to-analog converter (DAC) that generates a reference voltage based on an input code, and a voltage converter that converts an input voltage to an output voltage based on the reference voltage. A first adjustable reference circuit provides a first reference signal to the DAC and a second adjustable reference circuit provides a second reference signal to the DAC. Control circuitry adjusts the first adjustable reference circuit to perform gain trimming of the output voltage and adjusts the second adjustable reference circuit to perform offset trimming of the output voltage. A calibration procedure includes adjusting for both gain and offset, with a two-step approach for positive offset conditions—first incrementing the input code to create a negative offset, then performing offset trimming.
STMicroelectronics Asia Pacific Pte Ltd. (Singapore)
Inventor
Sautto, Marco
Fucili, Giona
Lo Muzzo, Valerio
Linggajaya, Kaufik
Abstract
In accordance with an embodiment, a method of operating a piezoelectric transducer configured to transduce mechanical vibrations into transduced electrical signals at a pair of sensor electrodes includes stimulating a resonant oscillation of the piezoelectric transducer by applying at least one pulse electrical stimulation signal to the pair of sensor electrodes; detecting, at the pair of sensor electrodes, at least one electrical signal resulting from the stimulated resonant oscillation, wherein the at least one electrical signal resulting from the stimulated resonant oscillation oscillates at a resonance frequency of the piezoelectric transducer; measuring a frequency of oscillation of the at least one electrical signal resulting from the stimulated resonant oscillation to obtain a measured resonance frequency of the piezoelectric transducer; and tuning a stopband frequency of a notch filter coupled to the piezoelectric transducer to match the measured resonance frequency of the piezoelectric transducer.
An embodiment is a method including receiving, by a first device via a mesh communication network, a first broadcast message over a first communication channel, the first broadcast message having a first hop count, receiving, by the first device via the mesh communication network, a second broadcast message over the first communication channel, and determining, by the first device, whether the second broadcast message is a consistent broadcast message with the first broadcast message, the determining including determining, by the first device, whether the first broadcast message has a same originator address as the second broadcast message, and determining, by the first device, whether the second hop count is larger than the first hop count.
A process for manufacturing a vertical conduction MOSFET device including a body of silicon carbide having a first conductivity type and a face. A metallization region extends on the face of the body. A body region of a second conductivity type extends in the body, from the face of the body, along a first direction parallel to the face and along a second direction transverse to the face. A source region of the first conductivity type extends towards the inside of the body region, from the face of the body, and has a first portion and a second portion. The first portion has a first doping level and extends in direct electrical contact with the metallization region. The second portion has a second doping level and extends in direct electrical contact with the first portion of the source region. The second doping level is lower than the first doping level.
H10D 62/13 - Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H10D 62/17 - Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
STMICROELECTRONICS RESEARCH & DEVELOPMENT) LIMITED (United Kingdom)
Inventor
Raynor, Jeffrey M.
Moeneclaey, Nicolas
Abstract
The present disclosure relates to a sensor having pixels, each pixel having photodiodes having each a terminal coupled to a first node associated with the photodiode; and an amplifier having a first part and, for each photodiode, a second part associated with the photodiode. The first part includes an output of the amplifier and a first MOS transistor of a differential pair. Each second part includes a second MOS transistor of the differential pair having its gate coupled to the first node associated with the photodiode the second part is associated with; a first switch coupling a source of the second transistor to the first part of the amplifier; and a second switch coupling a drain of the second transistor to the first part of the amplifier.
The present description concerns a device including phase-change memory cells, each memory cell including a first resistive element in lateral contact with a second element made of a phase-change material.
The present disclosure is directed to a package that includes a plurality of die that are stacked on each other. The plurality of die are within a first resin and conductive layer is on the first resin. The conductive layer is coupled between ones of first conductive vias extending into the first resin to corresponding ones of the plurality of die. The conductive layer and the first conductive vias couple ones of the plurality of die to each other. A second conductive via extends into the first resin to a contact pad of the substrate, and the conductive layer is coupled to the second conductive via coupling ones of the plurality of die to the contact pad of the substrate. A second resin is on and covers the first resin and the conductive layer on the first resin. In some embodiments, the first resin includes a plurality of steps (e.g., a stepped structure). In some embodiments, the first resin includes inclined surfaces (e.g., sloped surfaces).
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
The present description concerns a method of manufacturing a device comprising at least one radio frequency component on a semiconductor substrate comprising: a) a laser anneal of a first thickness of the substrate on the upper surface side of the substrate; b) the forming of an insulating layer on the upper surface of the substrate; and c) the forming of said at least one radio frequency component on the insulating layer.
An inertial structure is elastically coupled through a first elastic structure to a supporting structure so as to move along a sensing axis as a function of a quantity to be detected. The inertial structure includes first and second inertial masses which are elastically coupled together by a second elastic structure to enable movement of the second inertial mass along the sensing axis. The first elastic structure has a lower elastic constant than the second elastic structure so that, in presence of the quantity to be detected, the inertial structure moves in a sensing direction until the first inertial mass stops against a stop structure and the second elastic mass can move further in the sensing direction. Once the quantity to be detected ends, the second inertial mass moves in a direction opposite to the sensing direction and detaches the first inertial mass from the stop structure.
G01P 15/125 - Measuring accelerationMeasuring decelerationMeasuring shock, i.e. sudden change of acceleration by making use of inertia forces with conversion into electric or magnetic values by capacitive pick-up
B81C 1/00 - Manufacture or treatment of devices or systems in or on a substrate
G01P 15/08 - Measuring accelerationMeasuring decelerationMeasuring shock, i.e. sudden change of acceleration by making use of inertia forces with conversion into electric or magnetic values
The present disclosure is directed to a device and method for lid angle detection that is accurate even if the device is activated in an upright position. While the device is in a sleep state, first and second sensor units measure acceleration and angular velocity, and calculate orientations of respective lid components based on the acceleration and angular velocity measurements. Upon the device exiting the sleep state, a processor estimates the lid angle using the calculated orientations, sets the estimated lid angle as an initial lid angle, and updates the initial lid angle using, for example, two accelerometers; two accelerometers and two gyroscopes; two accelerometers and two magnetometers; or two accelerometers, two gyroscopes, and two magnetometers.
G01C 9/08 - Means for compensating acceleration forces due to movement of instrument
G01C 19/5705 - Turn-sensitive devices using vibrating masses, e.g. vibratory angular rate sensors based on Coriolis forces using masses driven in reciprocating rotary motion about an axis
G01P 3/44 - Devices characterised by the use of electric or magnetic means for measuring angular speed
G06F 1/3246 - Power saving characterised by the action undertaken by software initiated power-off
H04M 1/02 - Constructional features of telephone sets
Generally described, one or more embodiments are directed to semiconductor packages comprising a plurality of leads and methods of forming same. The plurality of leads include active leads that are electrically coupled to bond pads of a semiconductor die and thereby coupled to active components of the semiconductor die, and inactive leads that are not electrically coupled to bond pads of the semiconductor die. The active leads have surfaces that are exposed at a lower surface of the semiconductor package and forms lands, while the inactive leads are not exposed at the lower surface of the package.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
Generally described, one or more embodiments are directed to semiconductor packages comprising a plurality of leads and methods of forming same. The plurality of leads include active leads that are electrically coupled to bond pads of a semiconductor die and thereby coupled to active components of the semiconductor die, and inactive leads that are not electrically coupled to bond pads of the semiconductor die. The active leads have surfaces that are exposed at a lower surface of the semiconductor package and forms lands, while the inactive leads are not exposed at the lower surface of the package.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
The present disclosure is directed to embodiments of optical sensor packages. For example, at least one embodiment of an optical sensor package includes a light-emitting die, a light-receiving die, and an interconnect substrate within a first resin. A first transparent portion is positioned on the light-emitting die and the interconnect substrate, and a second transparent portion is positioned on the light-receiving die and the interconnect substrate. A second resin is on the first resin, the interconnect substrate, and the first and second transparent portions, respectively. The second resin partially covers respective surfaces of the first and second transparent portions, respectively, such that the respective surfaces are exposed from the second resin.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
A blind opening is formed in a bottom surface of a semiconductor substrate to define a thin membrane suspended from a substrate frame. The thin membrane has a topside surface and a bottomside surface. A stress structure is mounted to one of the topside surface or bottomside surface of the thin membrane. The stress structure induces a bending of the thin membrane which defines a normal state for the thin membrane. Piezoresistors are supported by the thin membrane. In response to an applied pressure, the thin membrane is bent away from the normal state and a change in resistance of the piezoresistors is indicative of the applied pressure.
B81B 3/00 - Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes
G01L 1/18 - Measuring force or stress, in general using properties of piezo-resistive materials, i.e. materials of which the ohmic resistance varies according to changes in magnitude or direction of force applied to the material
G01L 9/00 - Measuring steady or quasi-steady pressure of a fluid or a fluent solid material by electric or magnetic pressure-sensitive elementsTransmitting or indicating the displacement of mechanical pressure-sensitive elements, used to measure the steady or quasi-steady pressure of a fluid or fluent solid material, by electric or magnetic means
97.
ENHANCHED THERMAL DISSIPATION IN FLIP-CHIP SEMICONDUCTOR DEVICES USING LASER DIRECT (LDS) STRUCTURING TECHNOLOGY
A device includes a leadframe with a semiconductor die having a first side facing and electrically coupled to the leadframe and a second side facing away from the leadframe. An encapsulation body containing laser direct structuring (LDS) material covers the semiconductor die and has an outer surface opposite the leadframe. Metal vias are formed through the LDS material between the outer surface and the second side of the semiconductor die, and a metal pad is formed at the outer surface. The metal vias and pad create a thermal dissipation path. The semiconductor die may be mounted in a flip-chip configuration and connected to the leadframe through metal pillars. The metal vias and pad may be formed by laser-activating the LDS material followed by copper plating. The device can be configured as a Quad Flat No-leads (QFN) package, and a heat sink may be mounted on the metal pad.
H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
Methods and structures for forming highly-doped, ultrathin layers for transistors formed in semiconductor-on-insulator substrates are described. High dopant concentrations may be achieved in ultrathin semiconductor layers to improve device characteristics. Ion implantation at elevated temperatures may mitigate defect formation for stoichiometric dopant concentrations up to about 30%. In-plane stressors may be formed adjacent to channels of transistors formed in ultrathin semiconductor layers.
H10D 30/69 - IGFETs having charge trapping gate insulators, e.g. MNOS transistors
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
H01L 21/70 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereofManufacture of integrated circuit devices or of specific parts thereof
H10D 62/822 - Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
H10D 86/00 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
A vertical semiconductor triode includes a first layer of semiconductor material, the first layer including first and second surfaces, the first surface being in contact with a first electrode forming a Schottky contact.
H10D 62/83 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
H10D 64/23 - Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
H10D 64/62 - Electrodes ohmically coupled to a semiconductor
COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES (France)
STMICROELECTRONICS (GRENOBLE 2) SAS (France)
STMicroelectronics (Crolles 2) SAS (France)
Inventor
Mulin, Raphael
Jeannin, Olivier
Deneuville, Francois
Abstract
The disclosure relates to an optoelectronic device comprising in a stack: one reflection polarizing filter, one phase-shifting element configured to add a π/4 phase shift in polarization, one active region, one reflector, so that the light radiation rays reflected by the reflector and passing through the phase-shifting element exhibit a new polarization phase-shifted by π/2 with respect to their initial polarization, the rays then being reflected anew by the polarizing filter in the direction of the active region.
