SANYO Semiconductor Co., Ltd.

Japan

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IPC Class
H01L 21/60 - Attaching leads or other conductive members, to be used for carrying current to or from the device in operation 6
G03B 5/00 - Adjustment of optical system relative to image or object surface other than for focusing of general interest for cameras, projectors or printers 4
H01L 23/02 - ContainersSeals 3
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate 3
H01L 33/62 - Arrangements for conducting electric current to or from the semiconductor body, e.g. leadframe, wire-bond or solder balls 3
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Found results for  patents

1.

BONDING DEVICE AND PROCESS FOR PRODUCTION OF SEMICONDUCTOR DEVICE USING SAME

      
Application Number JP2011051148
Publication Number 2011/118247
Status In Force
Filing Date 2011-01-17
Publication Date 2011-09-29
Owner
  • SANYO ELECTRIC CO., LTD. (Japan)
  • SANYO Semiconductor Co., Ltd. (Japan)
Inventor
  • Negishi Toshimori
  • Wakui Motoaki
  • Abe Satoshi

Abstract

Disclosed are: a bonding device which enables the easy confirmation of a passage of a gas to be supplied; and a process for producing a semiconductor device using the bonding device. The bonding device comprises a wire clamper (32), a capillary (30), a torch (33) and a nozzle (39). In the bonding device, the bonding of a wire is achieved while spraying an inert gas (42) onto a part to be joined on the wire through the nozzle (39). An optical fiber (41) which can emit a beam (40) along the direction of the blowing of the gas (42) is integrated in the inside of the nozzle (39). Therefore, it becomes possible to blow the gas (42) onto a pad (17) properly by so adjusting the position of the nozzle (39) that the pad (17), which corresponds to the part to be joined, can be irradiated with the beam (40) emitted from the optical fiber (41).

IPC Classes  ?

  • H01L 21/60 - Attaching leads or other conductive members, to be used for carrying current to or from the device in operation

2.

SUBSTRATE AND MANUFACTURING METHOD FOR CIRCUIT DEVICE USING SUBSTRATE

      
Application Number JP2010072825
Publication Number 2011/089806
Status In Force
Filing Date 2010-12-13
Publication Date 2011-07-28
Owner
  • SANYO ELECTRIC CO., LTD. (Japan)
  • SANYO Semiconductor Co., Ltd. (Japan)
Inventor
  • Mizutani Masahiko
  • Kusabe Takaya

Abstract

Disclosed is a substrate which can be easily separated from each mounting substrate in the final stage of the manufacturing process and a manufacturing method for a circuit device which uses the substrate. A substrate (10) comprises: a substrate region (24) which is configured from a plurality of mounting substrates (12); slits (30) which are provided by removing the substrate (10) in a groove shape along the boundary between mounting substrates (12); and first and second support sections (14, 16) which are disposed next to the edge of the substrate region (24) where the ends of the mounting substrates (12) in the longitudinal direction are located. Furthermore, a separation groove (20A) is formed at the boundary between the substrate region (24) and the first support section (14), and another separation groove (22A) is formed at the boundary between the substrate region (24) and the second support section (16).

IPC Classes  ?

3.

SUBSTRATE AND METHOD FOR MANUFACTURING CIRCUIT DEVICE THAT USE SAME

      
Application Number JP2010072826
Publication Number 2011/074684
Status In Force
Filing Date 2010-12-13
Publication Date 2011-06-23
Owner
  • SANYO ELECTRIC CO., LTD. (Japan)
  • SANYO Semiconductor Co., Ltd. (Japan)
Inventor
  • Mizutani Masahiko
  • Takakusaki Sadamichi
  • Yoshii Masurao

Abstract

Provided are a substrate configured so that the curving thereof in the middle stage of a conveyance step is minimized, and a method for manufacturing a circuit device which uses the substrate. A substrate (10) is provided with mounting substrates (12) which are elongated in the lateral direction, slits (30) which are provided between the mounting substrates (12), and connection sections (32) which connect sides of adjacent mounting substrates (12) together and have a smaller thickness than the mounting substrates (12). Connecting the longitudinal sides of the mounting substrates (12) by means of the connection sections (32) reduces the deflection of the mounting substrates (12) in the stage in which the substrate (10) is conveyed.

IPC Classes  ?

  • H05K 1/02 - Printed circuits Details
  • H05K 1/18 - Printed circuits structurally associated with non-printed electric components

4.

SUBSTRATE AND METHOD FOR MANUFACTURING CIRCUIT DEVICE USING SAME

      
Application Number JP2010068800
Publication Number 2011/049234
Status In Force
Filing Date 2010-10-19
Publication Date 2011-04-28
Owner
  • SANYO ELECTRIC CO., LTD. (Japan)
  • SANYO Semiconductor Co., Ltd. (Japan)
Inventor
  • Mizutani Masahiko
  • Takakusaki Sadamichi
  • Mori Haruhiko
  • Kusabe Takaya

Abstract

Provided are a substrate which is prevented from being bent during a transfer step, and a method for manufacturing a circuit device using the same. A substrate (10) is provided with a mounting substrate region (24) comprising a plurality of mounting substrates (12) disposed adjacent to each other, and a first support part (14) and a second support part (16) that are continuous with the plurality of mounting substrates (12). First separation grooves (30) are provided in boundary portions between the mounting substrates (12), and second separation grooves (32) are provided between the mounting substrates (12), and the first support part (14) and the second support part (16). By providing the first support part (14) and the second support part (16), the substrate (10) is prevented from being bent in the stage in which the substrate (10) is transferred.

IPC Classes  ?

  • H05K 1/02 - Printed circuits Details
  • H05K 3/00 - Apparatus or processes for manufacturing printed circuits

5.

LIGHT-EMITTING MODULE

      
Application Number JP2010067328
Publication Number 2011/040633
Status In Force
Filing Date 2010-09-28
Publication Date 2011-04-07
Owner
  • SANYO ELECTRIC CO., LTD. (Japan)
  • SANYO Semiconductor Co., Ltd. (Japan)
Inventor
  • Terauchi Masashi
  • Osumi Kazushige
  • Kusabe Takaya

Abstract

Disclosed is a compact light-emitting module provided with a light-emitting element and a power-source circuit. The light-emitting module (10) is principally provided with a first substrate (12), to the bottom surface of which the light-emitting element (18) is affixed; and a second substrate (14), within which a power-source circuit that supplies current to the light-emitting element (18) is embedded. Also, the first substrate (12) and the second substrate (14) are mechanically connected to each other, and form a configuration wherein a gap exists between the two. Furthermore, a metal substrate is used as the first substrate (12) in order for heat generated by the light-emitting element (18) during light emission to be favorably released to the outside. Meanwhile, a low-cost glass epoxy substrate is used as the second substrate (14), within which the power-source circuit is embedded.

IPC Classes  ?

  • H01L 33/54 - Encapsulations having a particular shape
  • F21S 2/00 - Systems of lighting devices, not provided for in main groups or , e.g. of modular construction
  • H01L 33/64 - Heat extraction or cooling elements
  • F21W 131/20 - Lighting for medical use
  • F21Y 101/02 - Miniature, e.g. light emitting diodes (LED)

6.

IMAGING DEVICE, IMAGING DEVICE CONTROL METHOD, AND IMAGING DEVICE CONTROL PROGRAM

      
Application Number JP2009066770
Publication Number 2011/036792
Status In Force
Filing Date 2009-09-28
Publication Date 2011-03-31
Owner
  • National University Corporation Kochi University (Japan)
  • SANYO Semiconductor Co., Ltd. (Japan)
  • MIZUHO IKAKOGYO CO., LTD. (Japan)
Inventor
  • Sato Takayuki
  • Kojima Kazuaki
  • Noguchi Katsumi

Abstract

Provided is a fluorescent endoscopic device or the like that does not require an optical filter and does not require special image signal processing for the purpose of color correction. In the structure of the device equipped with an excitation light radiation means (1), a radiation means drive means (3), a photoelectric conversion means (8) that converts fluorescent light generated by living tissue into an electrical signal, a photoelectric conversion element drive means (6) that determines the drive timing for the photoelectric conversion means (8), and a stored charge reset means (6) that resets a charge stored in the photoelectric conversion means (8), the excitation light radiation means (1) is driven intermittently, and when the excitation light radiation means (1) is not being driven, the photoelectric conversion element drive means (6) drives the photoelectric conversion means (6) to perform photoelectric conversion.

IPC Classes  ?

  • A61B 1/04 - Instruments for performing medical examinations of the interior of cavities or tubes of the body by visual or photographical inspection, e.g. endoscopesIlluminating arrangements therefor combined with photographic or television appliances
  • A61B 1/00 - Instruments for performing medical examinations of the interior of cavities or tubes of the body by visual or photographical inspection, e.g. endoscopesIlluminating arrangements therefor
  • H04N 5/225 - Television cameras
  • H04N 5/238 - Circuitry for compensating for variation in the brightness of the object by influencing optical part of the camera

7.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

      
Application Number JP2010053490
Publication Number 2010/113584
Status In Force
Filing Date 2010-02-25
Publication Date 2010-10-07
Owner
  • SANYO ELECTRIC CO., LTD. (Japan)
  • SANYO Semiconductor Co., Ltd. (Japan)
Inventor
  • Kato Takanori
  • Nakatsuka Isao

Abstract

A method for manufacturing a semiconductor device is provided with: a step of preparing a semiconductor wafer (22) in a state where the circumference of the semiconductor wafer, which has been divided into semiconductor device parts, is adhered on a dicing sheet (21) supported by a wafer ring (23); a step of fixing the wafer ring (23) after transferring the wafer ring to a table (14) where laser printing is to be performed; and a step of marking on the main surface where the semiconductor material of the semiconductor device parts which configure the semiconductor wafer (22) is exposed, by radiating laser beams through the dicing sheet and an adhesive layer.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 23/00 - Details of semiconductor or other solid state devices

8.

SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME

      
Application Number JP2010053487
Publication Number 2010/098500
Status In Force
Filing Date 2010-02-25
Publication Date 2010-09-02
Owner
  • SANYO ELECTRIC CO., LTD. (Japan)
  • SANYO Semiconductor Co., Ltd. (Japan)
Inventor
  • Kitazawa, Takashi
  • Sakamoto, Yasushige
  • Wakui, Motoaki

Abstract

A semiconductor element (10) is secured to an island (7), and a plurality of through-holes (8) are formed in the portion of the island (7), which surrounds the area to which the semiconductor element (10) is secured. Further, the electrode pads of the semiconductor element (10) and leads (4) are electrically connected by copper wires (11). In this structure, the cost of materials is reduced by using the copper wires (11) in comparison with gold wires. Further, a part of a resin package (2) is embedded in through-holes (8), so that the island (7) can be easily supported within the resin package (2).

IPC Classes  ?

  • H01L 23/50 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements for integrated circuit devices
  • H01L 21/60 - Attaching leads or other conductive members, to be used for carrying current to or from the device in operation

9.

SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING SAME

      
Application Number JP2010053489
Publication Number 2010/098501
Status In Force
Filing Date 2010-02-25
Publication Date 2010-09-02
Owner
  • SANYO ELECTRIC CO., LTD. (Japan)
  • SANYO Semiconductor Co., Ltd. (Japan)
Inventor
  • Watanabe Masakazu
  • Kuramochi Takashi
  • Hatanai Masahiro

Abstract

A semiconductor device (10) provided with: an island (12A) and an island (12B) which are separated from each other; leads (14) which approach the islands (12A, 12B) at one end; a control element (20) which is attached to the island (12A) and is connected to a lead (14E) through a thin metal wire (24C); and a switching element (18) which is attached to the island (12B) and is connected to the lead (14E) through a thin metal wire (26). Further, the thin metal wire (24C) and the thin metal wire (26) are arranged so as to intersect.

IPC Classes  ?

  • H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
  • H01L 21/60 - Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or

10.

ETCHANT COMPOSITION

      
Application Number JP2009071474
Publication Number 2010/082439
Status In Force
Filing Date 2009-12-24
Publication Date 2010-07-22
Owner
  • SANYO Semiconductor Manufacturing Co., Ltd. (Japan)
  • Hayashi Pure Chemical Ind, Ltd. (Japan)
  • SANYO ELECTRIC CO., LTD. (Japan)
  • Sanyo Semiconductor Co., Ltd. (Japan)
Inventor
  • Tago, Tsuguhiro
  • Matsuda, Tomotake
  • Kimura, Mayumi
  • Aoyama, Tetsuo

Abstract

An aqueous solution containing phosphoric acid, nitric acid, an organic acid salt, and a surfactant is used as an etchant composition for etching a metal film formed on a substrate.  The organic acid salt is at least one compound selected from a group consisting of the ammonium salts, amine salts, quaternary ammonium salts, and alkali metal salts of at least one acid selected from a group consisting of aliphatic monocarboxylic acids, aliphatic polycarboxylic acids, aliphatic hydroxycarboxylic acids, aromatic monocarboxylic acids, aromatic polycarboxylic acids, and aromatic hydroxycarboxylic acids.  The etchant composition is used in the case where the metal film is aluminum or an aluminum alloy.

IPC Classes  ?

  • C23F 1/20 - Acidic compositions for etching aluminium or alloys thereof
  • H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
  • H01L 21/308 - Chemical or electrical treatment, e.g. electrolytic etching using masks
  • H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layersAfter-treatment of these layers
  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • H01L 23/52 - Arrangements for conducting electric current within the device in operation from one component to another

11.

RECEIVER APPARATUS

      
Application Number JP2009068099
Publication Number 2010/050389
Status In Force
Filing Date 2009-10-21
Publication Date 2010-05-06
Owner SANYO SEMICONDUCTOR CO., LTD. (Japan)
Inventor
  • Taira, Masaaki
  • Matsumoto, Osamu
  • Nomoto, Katsumi
  • Inako, Kazuyoshi

Abstract

A receiver apparatus comprises: an audio signal generating unit that generates an audio signal from a received signal that is received via a tuner; a control signal output unit that outputs, based on the received signal, a control signal for use in controlling audio signal processing to which the audio signal is subjected; an audio signal processing unit that subjects the audio signal to the audio signal processing in accordance with the control signal; and a reception channel control unit that controls the reception channel of the tuner and acquires, based on the received signal, information related to the reception status of a reception channel. In accordance with instructions from a general control unit that is configured to generally control the audio signal generating unit, control signal output unit, audio signal processing unit and reception channel control unit, the reception channel control unit stores the control signal, which is based on the received signal of a first reception channel, when switching the reception channel from the first reception channel to a second reception channel, and outputs the stored control signal to the audio signal processing unit when switching the reception channel back to the first reception channel.

IPC Classes  ?

12.

VIBRATION CORRECTION CONTROL CIRCUIT AND IMAGING DEVICE COMPRISING SAME

      
Application Number JP2009063244
Publication Number 2010/013647
Status In Force
Filing Date 2009-07-24
Publication Date 2010-02-04
Owner
  • SANYO ELECTRIC CO.,LTD. (Japan)
  • SANYO SEMICONDUCTOR CO., LTD. (Japan)
Inventor
  • Yamada, Yoshihisa
  • Kamiya, Tomonori

Abstract

The present invention comprises: an analog/digital conversion means for converting vibration detection signals output from a vibration detection element that detects vibrations of an imaging device into digital signals; a gyro filter that obtains the amount of movement of the imaging device based on the vibration detection signals digitalized by the analog/digital conversion means; a rotation control means for generating an amount of rotary drive in a stepping motor based on both the current position and amount of movement of an optical component or an imaging element; and a stepping control means for generating and outputting pulse signals that drive the rotation of the stepping motor in each phase according to the amount of rotary drive, wherein the stepping control means enables pulse-width modulation of the ratio between the periods in which high-level pulse signals and low-level pulse signals are respectively applied to the same phase of the stepping motor.

IPC Classes  ?

  • G03B 5/00 - Adjustment of optical system relative to image or object surface other than for focusing of general interest for cameras, projectors or printers
  • H04N 5/232 - Devices for controlling television cameras, e.g. remote control

13.

SEMICONDUCTOR DEVICE

      
Application Number JP2009060416
Publication Number 2009/148180
Status In Force
Filing Date 2009-06-02
Publication Date 2009-12-10
Owner
  • SANYO ELECTRIC CO., LTD. (Japan)
  • SANYO Semiconductor Co., Ltd. (Japan)
  • SANYO Semiconductor Manufacturing Co., Ltd. (Japan)
Inventor
  • Mita, Keiji
  • Takahashi, Masao
  • Arai, Takao

Abstract

Provided is a semiconductor device wherein device size is reduced and a leak current to a substrate is eliminated.  P-type diffusion layers (18-22) as a collector region are arranged so as to partition an emitter region.  The P-type diffusion layer (22) is formed with an impurity concentration lower than that of the P-type diffusion layers (18-22) and a diffusion width narrower than that of the P-type diffusion layers.  With such structure, current performance is improved, while increasing an effectively functioning emitter region, and reducing the device size.  The leak current to the substrate is eliminated by having a desired parasitic transistor operate in a positive manner.

IPC Classes  ?

  • H01L 21/331 - Transistors
  • H01L 21/8222 - Bipolar technology
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 29/732 - Vertical transistors

14.

VIBRATION CORRECTION CONTROL CIRCUIT AND IMAGING DEVICE USING THE SAME

      
Application Number JP2009057676
Publication Number 2009/131054
Status In Force
Filing Date 2009-04-16
Publication Date 2009-10-29
Owner
  • SANYO ELECTRIC CO., LTD. (Japan)
  • SANYO Semiconductor Co., Ltd. (Japan)
Inventor Iwata, Naoto

Abstract

If a hand-vibration correction function is resumed in a state that a lens is apart from the center position after a panning state or a tilting state is terminated, the movable range in a direction of the shift of the lens from the center position is narrowed. An integration circuit (36) integrates an acceleration signal outputted from a vibration detection element (60) and generates a shift amount signal indicating the shift amount of an imaging device. A control unit (31) judges whether the device is in the panning state or the tilting state. The integration circuit (36) is formed by a digital filter, which includes a register for holding an accumulation value to be an amplitude value of the shift amount signal. The control unit (31) decreases the absolute value of the accumulation value held in the register if it is judged that the device is in the panning state or the tilting state.

IPC Classes  ?

  • H04N 5/232 - Devices for controlling television cameras, e.g. remote control
  • G03B 5/00 - Adjustment of optical system relative to image or object surface other than for focusing of general interest for cameras, projectors or printers
  • H04N 101/00 - Still video cameras

15.

VIBRATION CORRECTION CONTROL CIRCUIT AND IMAGING DEVICE USING THE SAME

      
Application Number JP2009057678
Publication Number 2009/131056
Status In Force
Filing Date 2009-04-16
Publication Date 2009-10-29
Owner
  • SANYO ELECTRIC CO., LTD. (Japan)
  • SANYO Semiconductor Co., Ltd. (Japan)
Inventor Iwata, Naoto

Abstract

It is possible to suppress hypersensitive reaction of a lens or an imaging element to an acceleration signal while the accumulation value of the acceleration signal outputted from a vibration detection element is small. An integration circuit (36) integrates an acceleration signal outputted from a vibration detection element (60) and generates a shift amount signal indicating the shift amount of an imaging device. The integration circuit (36) is formed by a digital filter, which includes a register for holding an accumulation value serving as a shift amount signal. A control unit (31) acquires an accumulation values held in the register at a predetermined interval and obtains a change amount between the accumulation value previously obtained and the accumulation value currently obtained. When the change value exceeds a predetermined threshold value, the control unit (31) subtracts a correction value from the currently obtained accumulation value so that the value approaches zero and resets the obtained value in the register.

IPC Classes  ?

  • H04N 5/232 - Devices for controlling television cameras, e.g. remote control
  • G03B 5/00 - Adjustment of optical system relative to image or object surface other than for focusing of general interest for cameras, projectors or printers
  • H04N 101/00 - Still video cameras

16.

VIBRATION CORRECTION CONTROL CIRCUIT AND IMAGING DEVICE USING THE SAME

      
Application Number JP2009057677
Publication Number 2009/131055
Status In Force
Filing Date 2009-04-16
Publication Date 2009-10-29
Owner
  • SANYO ELECTRIC CO., LTD. (Japan)
  • SANYO Semiconductor Co., Ltd. (Japan)
Inventor Iwata, Naoto

Abstract

If it is erroneously judged that a panning state or a tilting state in which a hand-vibration correction function does not operate is terminated, at least a apart of a camera operation intentionally applied by a user is cancelled. An integration circuit (36) integrates an acceleration signal outputted from a vibration detection element (60) and generates a shift amount signal indicating the shift amount of an imaging device. A control unit (31) samples a plurality of amplitude values of an acceleration signal during a predetermined unit period in the panning state or the tilting state. When an average value of the sampling values exists nearer to zero than a predetermined basic threshold value, it is judged that the panning state or the tilting state is terminated.

IPC Classes  ?

  • H04N 5/232 - Devices for controlling television cameras, e.g. remote control
  • G03B 5/00 - Adjustment of optical system relative to image or object surface other than for focusing of general interest for cameras, projectors or printers
  • H04N 101/00 - Still video cameras

17.

MOTOR DRIVE DEVICE

      
Application Number JP2008052344
Publication Number 2009/101676
Status In Force
Filing Date 2008-02-13
Publication Date 2009-08-20
Owner
  • Sanyo Electric Co., Ltd. (Japan)
  • Sanyo Semiconductor Co., Ltd. (Japan)
Inventor
  • Arai, Mitsuji
  • Oike, Takeshi

Abstract

A motor drive device is provided with a switching element controlling current flowing in a first coil of a stepping motor having first and second coils, which are electromagnetically coupled, a rectification element conducted toward the second coil from a ground-side, a coil current detecting part detecting current flowing in the first coil, a regenerative current detecting part detecting current flowing in the rectification element, a control part turning on the switching element at prescribed intervals and turning off the switching element when current flowing in the first coil reaches prescribed setting current based on a detection result in the coil current detecting part and a negative current detecting part detecting whether negative current whose absolute value is larger than a prescribed setting value flows in the rectification element or not when the switching element is turned off after it is turned on. The control part keeps the switching element by leaving it OFF when negative current does not flow based on a detection result of the negative current detecting part.

IPC Classes  ?

  • H02P 8/38 - Protection against faults, e.g. against overheating or step-outIndicating faults the fault being step-out
  • H02P 8/12 - Control or stabilisation of current

18.

MOTOR DRIVING CIRCUIT, FAN MOTOR, ELECTRONIC INSTRUMENT, AND NOTEBOOK PERSONAL COMPUTER

      
Application Number JP2007074947
Publication Number 2009/081496
Status In Force
Filing Date 2007-12-26
Publication Date 2009-07-02
Owner
  • Sanyo Electric Co., Ltd. (Japan)
  • Sanyo Semiconductor Co., Ltd. (Japan)
Inventor
  • Imai, Toshiyuki
  • Yoshitomi, Tetsuya
  • Noie, Joji

Abstract

A motor driving circuit includes a pulse generation circuit for generating pulse signals in which a duty ratio of one of logic levels increases as driving voltage in response to target rotation speed of a motor increases, and a drive control circuit for driving the motor by the driving voltage with a duty ratio higher than that of the pulse signal when the motor starts rotating from a halt based on a rotation signal according to rotation of the motor and driving the motor by the driving voltage for a period when the pulse signal remains at one of the logic levels after the motor starts to rotate.

IPC Classes  ?

  • H02P 6/08 - Arrangements for controlling the speed or torque of a single motor

19.

INSULATING GATE BIPOLAR TRANSISTOR

      
Application Number JP2008072114
Publication Number 2009/069834
Status In Force
Filing Date 2008-11-28
Publication Date 2009-06-04
Owner
  • SANYO ELECTRIC CO., LTD. (Japan)
  • SANYO SEMICONDUCTOR CO., LTD. (Japan)
Inventor
  • Okada, Kikuo
  • Hosoya, Takumi

Abstract

Fluctuation of switching characteristics of an insulating gate bipolar transistor (IGBT) having an NPT (Non Punch Through) structure is suppressed. In the IGBT, in a region (A) not covered with an interlayer insulating film (9) in a region between trenches (2, 2) adjacent to each other, a P type base region (4) and an N+ type emitter region (7) are formed, and a PN junction composed of an N- type drift layer (3) and a base layer (4) is formed. In a region (B) covered with the interlayer insulating film (9), since the base region (4) is not formed, an PN junction is not formed. Thus, in the region (B), floating state of the base region (4) is not generated.

IPC Classes  ?

  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect

20.

DMOS TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME

      
Application Number JP2008068113
Publication Number 2009/041741
Status In Force
Filing Date 2008-09-26
Publication Date 2009-04-02
Owner
  • SANYO ELECTRIC CO., LTD. (Japan)
  • SANYO SEMICONDUCTOR CO., LTD. (Japan)
Inventor
  • Takeda, Yasuhiro
  • Otake, Seiji
  • Kikuchi, Shuichi

Abstract

When a body layer is formed by oblique ion implantation in a DMOS transistor, leak current is reduced and the source-drain breakdown voltage is enhanced when the transistor is turned off. After forming a photoresist layer (18), a first ion implantation is performed from a first direction shown by the arrow A' toward the first corner (14C1) on the inside of a gate electrode (14) by using the photoresist layer (18) and the gate electrode (14) as a mask. A first body layer (17A') is formed by the first ion implantation. The first body layer (17A') is formed to extend from the first corner (14C1) to the below the gate electrode (14), and a higher P type impurity concentration can be secured in the body layer (17A') at the first corner (14C1) as compared with prior art transistors.

IPC Classes  ?

  • H01L 21/336 - Field-effect transistors with an insulated gate
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

21.

CHARGE PUMP TYPE BOOSTER CIRCUIT

      
Application Number JP2008064903
Publication Number 2009/028394
Status In Force
Filing Date 2008-08-21
Publication Date 2009-03-05
Owner
  • SANYO ELECTRIC CO., LTD. (Japan)
  • SANYO SEMICONDUCTOR CO., LTD. (Japan)
Inventor Ogata, Takashige

Abstract

Intended is to provide a charge pump type booster circuit, in which a regulator for generating a voltage of non-integer times from a voltage of integer times has to be so constituted as can withstand a high voltage in case an output voltage (VOUT) of non-integer times as high as an input voltage (VIN) is to be generated. The boosted output voltage (VOUT) is divided by resistors (R1, R2). An operation amplifier (A) controls the amplitudes of the drive clocks of condenser drive circuits (30, 32) with an output voltage (VA) so that a divided voltage (VB) may be VREF. As a result, the output voltage (VOUT) is subjected to a feedback control, and the voltage (VREF) and the voltage (VOUT) of non-integer times set according to a resistance ratio (R1/R2) are extracted from an output terminal (NOUT).

IPC Classes  ?

  • H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode

22.

LUMINESCENT MODULE, AND ITS MANUFACTURING METHOD

      
Application Number JP2008066130
Publication Number 2009/028738
Status In Force
Filing Date 2008-08-28
Publication Date 2009-03-05
Owner
  • SANYO ELECTRIC CO., LTD. (Japan)
  • SANYO Semiconductor Co., Ltd. (Japan)
  • TOTTORI SANYO ELECTRIC CO., LTD. (Japan)
Inventor
  • Takakusaki, Sadamichi
  • Motoike, Tatsuya
  • Matsumoto, Akihisa

Abstract

Provided are a luminescent module, which is improved in the heat radiation and in the contact between a sealing resin for sealing a light emitting element and another member, and a method for manufacturing the module. The luminescent module (10) comprises a metal substrate (12), a recess (18) formed by recessing the upper face of the metal substrate (12) partially, a light emitting element (20) housed in the recess (18), and a sealing resin (32) for covering the light emitting element (20). On the upper face of a metal substrate (40) in the region enclosing the recess (18), moreover, there is formed a rising portion (11), with which the sealing resin (32) comes into contact, thereby to improve the contact strength between the sealing resin (32) and the metal substrate (12).

IPC Classes  ?

  • H01L 33/32 - Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
  • H01L 33/56 - Materials, e.g. epoxy or silicone resin
  • H01L 33/60 - Reflective elements
  • H01L 33/62 - Arrangements for conducting electric current to or from the semiconductor body, e.g. leadframe, wire-bond or solder balls
  • H01L 33/64 - Heat extraction or cooling elements

23.

ETCHING SOLUTION COMPOSITION

      
Application Number JP2008062837
Publication Number 2009/011363
Status In Force
Filing Date 2008-07-16
Publication Date 2009-01-22
Owner
  • Hayashi Pure Chemical Ind, Ltd. (Japan)
  • SANYO ELECTRIC CO., LTD. (Japan)
  • SANYO Semiconductor Manufacturing Co., Ltd. (Japan)
  • Sanyo Semiconductor Co., Ltd. (Japan)
Inventor
  • Tago, Tsuguhiro
  • Matsuda, Tomotake
  • Kimura, Mayumi
  • Aoyama, Tetsuo

Abstract

The object is to etch a metal film (e.g., an aluminum film, an aluminum alloy film) with good controllability while preventing or inhibiting the occurrence of resist bleeding, thereby producing a metal film having the intended tapered shape and excellent flatness. An aqueous solution containing phosphoric acid, nitric acid and an organic acid salt is used as an etching solution composition for etching a metal film on a substrate. The organic acid salt used may be at least one member selected from the group consisting of an ammonium salt, an amine salt, a quaternary ammonium salt and an alkali metal salt of at least one member selected from the group consisting of an aliphatic monocarboxylic acid, an aliphatic polycarboxylic acid, an aliphatic oxycarboxylic acid, an aromatic monocarboxylic acid, an aromatic polycarboxylic acid and an aromatic oxycarboxylic acid. The organic acid salt is used at a concentration ranging from 0.1 to 20 wt%. The etching solution composition can be used when the metal film is made of aluminum or an aluminum alloy.

IPC Classes  ?

  • H01L 21/308 - Chemical or electrical treatment, e.g. electrolytic etching using masks

24.

MOTOR CONTROL CIRCUIT, FAN MOTOR, ELECTRONIC EQUIPMENT AND NOTEBOOK-SIZED PERSONAL COMPUTER

      
Application Number JP2007075104
Publication Number 2008/129747
Status In Force
Filing Date 2007-12-27
Publication Date 2008-10-30
Owner
  • Sanyo Electric Co., Ltd. (Japan)
  • Sanyo Semiconductor Co., Ltd. (Japan)
Inventor
  • Yoshitomi, Tetsuya
  • Noie, Joji
  • Imai, Toshiyuki

Abstract

A rotation control circuit for controlling a motor rotation in accordance with a rotation control signal for controlling of motor rotation and a rotational position detection signal from a hall element capable of detecting the rotational position of the motor is coupled with a hall element control circuit designed to when the rotation control signal is generated, apply an electric power source voltage for hall element to the hall element and to when the rotation control signal is not generated, halts the application of electric power source voltage for hall element to the hall element.

IPC Classes  ?

  • H02P 6/08 - Arrangements for controlling the speed or torque of a single motor

25.

ELECTRODE STRUCTURE AND SEMICONDUCTOR DEVICE

      
Application Number JP2008057127
Publication Number 2008/126914
Status In Force
Filing Date 2008-04-04
Publication Date 2008-10-23
Owner
  • SANYO ELECTRIC CO., LTD. (Japan)
  • SANYO SEMICONDUCTOR CO., LTD. (Japan)
Inventor
  • Okada, Kikuo
  • Kameyama, Kojiro
  • Oikawa, Takahiro

Abstract

A source electrode is formed to be connected to a plurality of source regions formed on the main surface, for instance, in a power MOS transistor. As nonuniform current densities are generated based on resistance in the in-plane direction of the source electrode, the number of wires for connecting the source and leads has been required to be increased. An electrode structure of this invention is composed of a copper plating layer (10e) formed on a pad electrode (10a) by electrolytic plating, a nickel plating layer (10f) formed by electroless plating to cover the upper surface and the side surface of the copper plating layer (10e), and a gold plating layer.

IPC Classes  ?

  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layersAfter-treatment of these layers
  • H01L 21/60 - Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
  • H01L 23/52 - Arrangements for conducting electric current within the device in operation from one component to another
  • H01L 29/41 - Electrodes characterised by their shape, relative sizes or dispositions
  • H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched

26.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

      
Application Number JP2008051884
Publication Number 2008/123020
Status In Force
Filing Date 2008-01-30
Publication Date 2008-10-16
Owner
  • SANYO ELECTRIC CO., LTD. (Japan)
  • SANYO SEMICONDUCTOR CO., LTD. (Japan)
Inventor Noma, Takashi

Abstract

To provide a semiconductor device which is low in manufacturing cost and provided with a smaller light emitting element, and to provide a method for manufacturing such semiconductor device. On the surface of a semiconductors substrate (6), a bonding layer (9) and a conductive paste (10a, 10b) are selectively applied. Then, on the semiconductor substrate (6), a light emitting element (LED chip (4)) is formed. A P-type semiconductor layer (3) is connected to the conductive paste (10a), and an N-type semiconductor layer (2) is connected to the conductive paste (10b). Thus, the LED chip (4) is electrically connected to the pad electrodes (8a, 8b) through the conductive paste (10a, 10b). On the semiconductor substrate (6), a protection layer (12) having an opening section at a position that corresponds to each of the pad electrodes (8a, 8b) is formed. On the pad electrodes (8a, 8b, 8c) in the opening, an electrode connecting layer (13) and a conductive terminal (14) are formed. Then, the protection layer (12), semiconductor substrate (6) and the like are cut along a prescribed dicing line (DL), and divided into separated chips.

IPC Classes  ?

  • H01L 31/12 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto
  • H01L 33/48 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor body packages
  • H01L 33/62 - Arrangements for conducting electric current to or from the semiconductor body, e.g. leadframe, wire-bond or solder balls

27.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

      
Application Number JP2007069426
Publication Number 2008/117488
Status In Force
Filing Date 2007-09-27
Publication Date 2008-10-02
Owner
  • SANYO ELECTRIC CO., LTD (Japan)
  • SANYO Semiconductor Co., Ltd (Japan)
Inventor Nakazato, Isao

Abstract

A thin semiconductor device in which the loop height of a thin metal wire is lowered furthermore as compared with prior art. The semiconductor device has such a structure as the bonding pad (55) and the electrode (53B) of a semiconductor chip (54) are connected via a thin metal wire (51). The thin metal wire (51) draws a curve (57) from a first bond and has a second linear extension (60) through a bend (59) at the end of the curved portion (57).

IPC Classes  ?

  • H01L 21/60 - Attaching leads or other conductive members, to be used for carrying current to or from the device in operation

28.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

      
Application Number JP2008055027
Publication Number 2008/114806
Status In Force
Filing Date 2008-03-12
Publication Date 2008-09-25
Owner
  • SANYO ELECTRIC CO., LTD. (Japan)
  • SANYO SEMICONDUCTOR CO., LTD. (Japan)
Inventor Kameyama, Kojiro

Abstract

In the case of forming a thin film semiconductor device by polishing a wafer, the rear surface of each chip must have been separately processed independently by being divided into chips. In this invention, the front surface of a wafer (2a) is bonded on a rigid supporting body (5) through a bonding layer (6), in a status where a groove section (4) is formed on the front surface of the wafer (2a) by half dicing. Then, after polishing the rear surface of the wafer (2a) and dividing the wafer into each chip (2b), rear surface processing, including heat treatment for forming a rear surface electrode (9a) and the like, is performed without separating the chip (2b) from the supporting body (5).

IPC Classes  ?

  • H01L 21/301 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to subdivide a semiconductor body into separate parts, e.g. making partitions
  • H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
  • H01L 21/52 - Mounting semiconductor bodies in containers

29.

CAPACITANCE VARIATION DETECTING CIRCUIT AND SEMICONDUCTOR DEVICE

      
Application Number JP2008052287
Publication Number 2008/105234
Status In Force
Filing Date 2008-02-13
Publication Date 2008-09-04
Owner
  • SANYO ELECTRIC CO., LTD. (Japan)
  • SANYO SEMICONDUCTOR CO., LTD. (Japan)
Inventor
  • Suzuki, Tatsuya
  • Kaneta, Yasuhiro

Abstract

A hybrid IC is composed of a semiconductor chip where a capacitance sensor is provided and a semiconductor chip where a detecting circuit for detecting a variation of the capacitance is provided. The number of bonding wires needed for both semiconductor chips is reduced. The back of a sensor chip (50) is connected to electrodes on the surface of a support substrate on which the sensor chip (50) is mounted. The potential at one terminal (Ncb) of the capacitor (Cm) of the sensor is set at a reference potential. A pad for the other terminal (Ncd) is formed on the front of the sensor chip (50). In the detection circuit chip (52), a pad to serve as the connection terminal (Nd) of the capacitor (Cm), a bias circuit (54) connected to the terminal (Nd) and adapted to output a bias voltage for charging the capacitor (Cm), and a detecting circuit (56) connected to the terminal (Nd) through a capacitor (Cc) and adapted to detect a variation of the potential at the terminal (Ncd) of the capacitor (Cm) as an electric signal are provided. Both chips (50, 52) are interconnected through bonding wires between the pad of the terminal (Nd) and the pad of the terminal (Ncd).

IPC Classes  ?

  • H04R 3/00 - Circuits for transducers
  • G01D 5/24 - Mechanical means for transferring the output of a sensing memberMeans for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for convertingTransducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying capacitance
  • G01R 27/26 - Measuring inductance or capacitanceMeasuring quality factor, e.g. by using the resonance methodMeasuring loss factorMeasuring dielectric constants
  • H04R 19/04 - Microphones

30.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

      
Application Number JP2008051898
Publication Number 2008/093880
Status In Force
Filing Date 2008-01-30
Publication Date 2008-08-07
Owner
  • SANYO ELECTRIC CO., LTD. (Japan)
  • SANYO SEMICONDUCTOR CO., LTD. (Japan)
Inventor Noma, Takashi

Abstract

Provided are a semiconductor device which has low manufacturing cost, high reliability and small sizes and a method for manufacturing such semiconductor device. A light emitting element (LED chip (8)) is formed on a first substrate (1). A cathode electrode (10) connected to an N-type region of the LED chip (8) is formed between the first substrate (1) and the LED chip (8). Side surfaces of the LED chip (8) are covered with insulating layers (11). An anode electrode (12) extending to a P-type region of the LED chip (8) is formed along the outer circumference of the insulating layer (11) from the surface of the first substrate (1). On theside surfaces of the first substrate (1), wiring layers (18) electrically connected to the cathode electrode (10) and the anode electrode (12) are formed along the side surfaces of the first substrate (1). The wiring layers (18) extend onto the rear surface of the first substrate (1). On the rear surface of the first substrate (1), conductive terminals (22) electrically connected to the wiring layers (18) are formed through electrode connecting layers (20).

IPC Classes  ?

  • H01L 31/12 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto
  • H01L 33/44 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
  • H01L 33/48 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor body packages
  • H01L 33/62 - Arrangements for conducting electric current to or from the semiconductor body, e.g. leadframe, wire-bond or solder balls

31.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

      
Application Number JP2007069427
Publication Number 2008/081630
Status In Force
Filing Date 2007-09-27
Publication Date 2008-07-10
Owner
  • SANYO ELECTRIC CO., LTD. (Japan)
  • SANYO SEMICONDUCTOR CO., LTD. (Japan)
Inventor
  • Takano, Yasuhiro
  • Fukuda, Hirokazu
  • Mashita, Atsushi

Abstract

A semiconductor device in which overall thickness is reduced by suppressing the rising of a metal thin line and connection reliability is enhanced at the joint of the metal thin line and other member during resin sealing. A method for manufacturing such semiconductor device is also provided. The semiconductor device (10A) comprises electrodes (12A, 12B, 12C), a semiconductor chip (13) bonded to the upper surface of the electrode (12A) formed in the shape of island, a metal thin line (15A) connecting the semiconductor chip (13) and the electrode (12C), a metal thin line (15B) connecting the semiconductor chip (13) and the electrode (12B), and a sealing resin (11) supporting these elements mechanically by sealing them integrally. The metal thin lines (15A, 15B) have planar shape curved convexly toward the upstream of the flow of the sealing resin (11) to be injected.

IPC Classes  ?

  • H01L 21/60 - Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings

32.

CURRENT MIRROR CIRCUIT

      
Application Number JP2007074229
Publication Number 2008/078591
Status In Force
Filing Date 2007-12-17
Publication Date 2008-07-03
Owner
  • SANYO ELECTRIC CO., LTD. (Japan)
  • SANYO SEMICONDUCTOR CO., LTD. (Japan)
Inventor Hashimoto, Fuminori

Abstract

[PROBLEMS] To improve accuracy of a current mirror circuit. [MEANS FOR SOLVING PROBLEMS] A current mirror circuit includes a transistor (Q1) wherein a base and a collector are short-circuited, and a transistor (Q2) wherein a base is connected to the base of the transistor (Q1). The current mirror circuit also has a MOS-type compensation transistor wherein a gate is connected to the collector of the transistor (Q1), a source is connected to the bases of the first and the second transistors, and a drain is connected to a power supply. Thus, though a current corresponding to a current flowing in the transistor (Q1) is permitted to flow in the transistor (Q2), a base current is not required in the compensation transistor (Q5).

IPC Classes  ?

  • H03F 3/343 - DC amplifiers in which all stages are DC-coupled with semiconductor devices only
  • G05F 3/26 - Current mirrors

33.

NONCONTACT TRANSMISSION DEVICE

      
Application Number JP2007073050
Publication Number 2008/066110
Status In Force
Filing Date 2007-11-29
Publication Date 2008-06-05
Owner
  • ASKA ELECTRON CORPORATION (Japan)
  • SANYO ELECTRIC CO., LTD. (Japan)
  • SANYO SEMICONDUCTOR CO., LTD. (Japan)
Inventor
  • Takaishi, Konomu
  • Nohara, Kazunori

Abstract

A noncontact transmission device (100) is provided with a driver (106) for driving a coil (102); a system clock oscillator (110) for outputting a system clock (CK0); a monitoring clock oscillator (112) for outputting a monitoring clock (LF0) having a frequency lower than that of the system clock (CK0); and a control circuit (108). The control circuit (108) outputs a system clock oscillating control signal (S60) based on the monitoring clock (LF0) while being in a standby state and makes the system clock oscillator (110) intermittently output a system clock (CK0) in synchronization with the control signal (S60). In a period when the system clock (CK0) is being outputted, the coil (102) is driven by a driver control signal (SD) and whether a device (200) to which data is to be transmitted is arranged or not is detected.

IPC Classes  ?

  • H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
  • G06K 17/00 - Methods or arrangements for effecting co-operative working between equipments covered by two or more of main groups , e.g. automatic card files incorporating conveying and reading operations
  • H02J 17/00 - Systems for supplying or distributing electric power by electromagnetic waves
  • H04B 5/02 - Near-field transmission systems, e.g. inductive loop type using transceiver

34.

NONCONTACT TRANSMISSION DEVICE

      
Application Number JP2007073051
Publication Number 2008/066111
Status In Force
Filing Date 2007-11-29
Publication Date 2008-06-05
Owner
  • ASKA ELECTRON CORPORATION (Japan)
  • SANYO ELECTRIC CO., LTD. (Japan)
  • SANYO SEMICONDUCTOR CO., LTD. (Japan)
Inventor
  • Takaishi, Konomu
  • Nohara, Kazunori

Abstract

A noncontact transmission device (100) is provided with a monitoring clock oscillator (112) for outputting a monitoring clock (LF0) having a frequency lower than that of a system clock (CK0); a control circuit (108); a memory (114) having information (D) stored to be used by the control circuit (108); and a reset circuit (116). The control circuit (108) includes an internal storage circuit for storing the information (D) read out from the memory (114). The control circuit (108) reads out and updates the information (D) stored in the internal storage circuit from the memory (114) in an update cycle based on the monitoring clock (LF0). Furthermore, the control circuit (108) reads out the information (D), which is reset in a reset cycle longer than the update cycle based on the monitoring clock (LF0) and stored in the internal storage circuit each time the information is reset, from the memory (114) and updates the information.

IPC Classes  ?

  • H02J 17/00 - Systems for supplying or distributing electric power by electromagnetic waves
  • H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
  • H04B 5/02 - Near-field transmission systems, e.g. inductive loop type using transceiver

35.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

      
Application Number JP2007070399
Publication Number 2008/044801
Status In Force
Filing Date 2007-10-12
Publication Date 2008-04-17
Owner
  • SANYO ELECTRIC CO., LTD. (Japan)
  • SANYO Semiconductor Co., Ltd. (Japan)
Inventor
  • Okada, Kikuo
  • Kameyama, Kojiro

Abstract

Provided are a semiconductor device and a method for manufacturing the same. In semiconductor devices of the conventional technologies, the chip size is increased when a withstand voltage is increased. In the semiconductor device of this invention, an end of a pn junction section (5) of a collector region (2) and a base region (3) is formed of a mesa groove (6) made of a trench. Thus, the chip size is not increased even when the mesa groove (6) is deeply formed to increase the withstand voltage.

IPC Classes  ?

36.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

      
Application Number JP2007066707
Publication Number 2008/032566
Status In Force
Filing Date 2007-08-22
Publication Date 2008-03-20
Owner
  • SANYO ELECTRIC CO., LTD. (Japan)
  • SANYO SEMICONDUCTOR CO., LTD. (Japan)
Inventor
  • Morita, Yuichi
  • Noma, Takashi

Abstract

Provided is a technology of easily forming a desired bump electrode directly on a low portion formed by a step. An isolating layer (12) is formed for isolating pump electrode forming regions (11) one from the other. The isolating layer (12) is, for instance, a resist layer, and is formed by, for instance, exposure/development process. Each bump electrode forming region (11) is surrounded by a protecting layer (10), which covers the side surfaces of a semiconductor substrate (2), and the isolating layer (12). A printing mask (16) having an opening section (15) corresponding to the position of the bump electrode forming region (11) is arranged above the semiconductor substrate (2). A paste-like solder (17) is applied on the printing mask (16). The solder (17) is applied on a metal layer (9) by shifting a squeegee (18) at a constant speed. A bump electrode (19) is obtained by removing the printing mask (16) and heating, melting and recrystallizing the solder (17).

IPC Classes  ?

  • H01L 23/12 - Mountings, e.g. non-detachable insulating substrates

37.

SEMICONDUCTOR DEVICE

      
Application Number JP2007066704
Publication Number 2008/023827
Status In Force
Filing Date 2007-08-22
Publication Date 2008-02-28
Owner
  • SANYO ELECTRIC CO., LTD. (Japan)
  • SANYO SEMICONDUCTOR CO., LTD. (Japan)
Inventor
  • Okada, Kazuo
  • Kitagawa, Katsuhiko
  • Yamada, Hiroshi

Abstract

Provided is a semiconductor device which has reduced sizes, lower manufacturing cost by simplifying the manufacturing process and a cavity. A device element (3) is formed on the front surface of a semiconductor substrate (4), and a sealing body (1) is bonded on the semiconductor substrate (4) through a bonding layer (6). The main surface (rear surface) of the sealing body (1) facing the semiconductor substrate (4) is bent inward, and a fixed space (cavity (2)) is arranged between the sealing body (1) and the semiconductor substrate (4). Since the rear surface of the sealing body (1) is bent, the sealing body (1) can be used not only as a sealing member for the device element (3) but also as a plano-concave lens (opposite direction).

IPC Classes  ?

  • H01L 23/02 - ContainersSeals
  • H01L 27/14 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy
  • H01L 31/02 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof - Details

38.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

      
Application Number JP2007066699
Publication Number 2008/023824
Status In Force
Filing Date 2007-08-22
Publication Date 2008-02-28
Owner
  • SANYO ELECTRIC CO., LTD. (Japan)
  • SANYO SEMICONDUCTOR CO., LTD. (Japan)
Inventor
  • Yamada, Hiroshi
  • Kitagawa, Katsuhiko
  • Okada, Kazuo
  • Morita, Yuichi
  • Shinogi, Hiroyuki
  • Ishibe, Shinzo
  • Seki, Yoshinori
  • Noma, Takashi

Abstract

Disclosed is a semiconductor device having a smaller size, which can be produced at a reduced cost by simplifying the production process. Also disclosed is a method for manufacturing such a semiconductor device. Further disclosed is a semiconductor device having a cavity. A first supporting body (5) having a through hole (6) extending from the front surface to the back surface is bonded to the surface of a semiconductor substrate (2) through an adhesive layer (4). A device element (1) and a wiring layer (3) are formed on the surface of the semiconductor substrate (2). A second supporting body (7) is bonded onto the first supporting body (5) through an adhesive layer (8) in such a manner that the through hole (6) is covered by the second supporting body (7). The device element (1) is sealed in a cavity (9) which is surrounded by the semiconductor substrate (2), the first supporting body (5) and the second supporting body (7).

IPC Classes  ?

39.

SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD

      
Application Number JP2007066703
Publication Number 2008/023826
Status In Force
Filing Date 2007-08-22
Publication Date 2008-02-28
Owner
  • SANYO ELECTRIC CO., LTD. (Japan)
  • SANYO SEMICONDUCTOR CO., LTD. (Japan)
Inventor
  • Shinogi, Hiroyuki
  • Kitagawa, Katsuhiko
  • Okada, Kazuo
  • Yamada, Hiroshi

Abstract

It is possible to provide a semiconductor device and its manufacturing method capable of easily providing a cavity space in a particular region when bonding a semiconductor substrate to a support body via an adhesion layer. A resist layer is applied to the entire surface of the semiconductor substrate (2) and exposure is performed for transferring a pattern. Next, development is performed and a part of the resist layer is removed so as to form the resist layer into a plurality of columnar structures (4). Next, an adhesive such as epoxy resin is applied to the entire surface of the semiconductor substrate (2). The adhesive is collected around the columnar structures (4) by itself to form an adhesion layer (5). For this, by and large, the adhesion layer (5) is not layered in the cavity forming region. Next, a support body (6) is bonded via the columnar structures (4) and the adhesion layers (5). By the bonding of the support body (6), a cavity (7) is defined by the surrounding semiconductor substrate (2), the columnar structures (3), and the support body (6).

IPC Classes  ?

40.

SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD

      
Application Number JP2007065575
Publication Number 2008/018524
Status In Force
Filing Date 2007-08-02
Publication Date 2008-02-14
Owner
  • SANYO ELECTRIC CO., LTD. (Japan)
  • SANYO SEMICONDUCTOR CO., LTD. (Japan)
Inventor
  • Noma, Takashi
  • Morita, Yuichi
  • Yamada, Hiroshi
  • Okada, Kazuo
  • Kitagawa, Katsuhiko
  • Okubo, Noboru
  • Ishibe, Shinzo
  • Shinogi, Hiroyuki

Abstract

It is possible to provide a package-type semiconductor device capable of realizing a smaller-size device, its manufacturing method, a small-size layered-type semiconductor device, and its manufacturing method. A device element (1) is formed on a semiconductor substrate (2) and a pad electrode (4) is formed and electrically connected to the device element (1). A support body (7) is bonded via a bonding layer (6) to the surface of the semiconductor substrate (2). The support body (7) has a through hole (15) penetrating from the front surface to the rear surface of the support body (7), so that electrical connection can be made with other device via the through hole (15). Moreover, an indentation (12) is formed at a part of the front surface of the support body (7). For this, it is possible to arrange whole or a part of the other device and parts by using the space in the indentation (12). Moreover, when forming a layered-type semiconductor device, layering is performed in such a manner that a part of the semiconductor device (50) of the upper layer is engaged with the interior of the indentation (12).

IPC Classes  ?

  • H01L 23/12 - Mountings, e.g. non-detachable insulating substrates
  • H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers
  • H01L 25/11 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in subclass
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or