Implementations of semiconductor packages may include a substrate, a first die coupled on the substrate, and a lead frame coupled over the substrate. The lead frame may include a die attach pad. Implementations of semiconductor packages may also include a second die coupled on the die attach pad. The second die may overlap the first die.
A semiconductor device may include a first chip with a first wafer and a first dielectric layer, and a second chip that includes a second wafer and a second dielectric layer, the second chip having a backside surface and a frontside surface opposed to the backside surface and bonded to the first chip at the frontside surface to define a bond line between the first dielectric layer and the second dielectric layer. The semiconductor device may include a die seal layer on the backside surface having a die seal ground contact in contact with the second wafer, and an electrostatic discharge path that includes the die seal layer, the die seal ground contact, a first die seal in the first dielectric layer, a second die seal in the second dielectric layer, and a hybrid bond connecting the first die seal and the second die seal through the bond line.
Implementations of semiconductor devices may include a die coupled over a lead frame, a redistribution layer (RDL) coupled over the die, a first plurality of vias coupled between the RDL and the die, and a second plurality of vias coupled over and directly to the lead frame. The second plurality of vias may be adjacent to an outer edge of the semiconductor device and may be electrically isolated from the die.
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
In a general aspect, a method includes forming, in a semiconductor device layer disposed on a semiconductor substrate, an opening between a first semiconductor device stack included in the semiconductor device layer and a second semiconductor device stack included in the semiconductor device layer. The method also includes forming a trench in the semiconductor substrate between the first semiconductor device stack and the second semiconductor device stack, the trench corresponding with the opening. The method further includes filling the trench with a first dielectric material, thinning the semiconductor substrate to expose the first dielectric material and separate the semiconductor substrate into a first substrate portion and a second substrate portion, and forming a layer of a second dielectric material on the first substrate portion, the second substrate portion and the exposed first dielectric material.
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
5.
METHODS AND APPARATUS FOR A TIME-TO-DIGITAL CONVERTER
Various embodiments of the present technology may provide methods and apparatus for a time-to-digital converter. The time-to-digital converter may include a state machine that increments/decrements according to an input signal and a count value. The time-to-digital converter may further include a register to store the count value according to the input signal.
High Electron Mobility Transistors (HEMTs) are described with a circular gate. with a drain region disposed within the circular gates and circular source region disposed around the circular gates. The circular gate and the circular source region may form complete circles.
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
7.
Image Sensors Having Data Converters with Low Noise Comparators
An image sensor may include an array of imaging pixels arranged in rows and columns. Each column of pixels can be coupled to a column analog-to-digital converter (ADC) via a pixel output line. The column ADC can include a first low noise single-ended comparison stage, a second low noise single-ended comparison stage, a latch circuit, and a counter. The first low noise single-ended comparison stage may include one or more current source transistors, a voltage ramp generator, a common source amplifier transistor, one or more autozero components, one or more capacitors such as a noise filtering capacitor, and a voltage clamping circuit. The voltage ramp generator can output an increasing voltage ramp or a decreasing voltage ramp.
A semiconductor device (10) includes a substrate (12), a first semiconductor region (14A) of a first conductivity type over the substrate and a second semiconductor region (14B) of the first conductivity type over the first semiconductor region. A trench gate structure (280) is in the second semiconductor region. A first doped region (22) of a second conductivity type is in the first semiconductor region, wherein the first doped region and the first semiconductor region provide a first charge-balance region (142). A second doped region (23) of the second conductivity type is in the second semiconductor region and interposed between the trench gate structure and the first doped region. The second doped region and the second semiconductor region provide a second charge-balance region (143). The second doped region is self-aligned with the trench gate structure.
A method includes applying a sintering precursor material layer to each of a first surface and a second surface of a base layer, and assembling a precursor assembly of a substrate by coupling a first electrically conductive layer on the sinter precursor material layer on the first surface of the base layer and a second electrically conductive layer on the second surface of the sinter precursor material layer on a second surface of the base layer such that the base layer is disposed between the first leadframe and the second leadframe. The method further includes sinter bonding the first electrically conductive layer and the second electrically conductive layer to the base layer to form a sinter bonded substrate.
H01L 23/373 - Cooling facilitated by selection of materials for the device
B22F 7/06 - Manufacture of composite layers, workpieces, or articles, comprising metallic powder, by sintering the powder, with or without compacting of composite workpieces or articles from parts, e.g. to form tipped tools
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/473 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing liquids
H05K 7/20 - Modifications to facilitate cooling, ventilating, or heating
Implementations of the semiconductor package may include a first sidewall opposite a second sidewall, and a third sidewall opposite a fourth sidewall. Implementations of the semiconductor package may include a first lead and a second lead extending from the first sidewall and a first half-etched tie bar directly coupled to the first lead. An end of the first half-etched tie bar may be exposed on the third sidewall of the semiconductor package. Implementations of the semiconductor package may also include a second half-etched tie bar directly coupled to the second lead. An end of the second half-etched tie bar may be exposed on the fourth sidewall. An end of the first lead and an end of the second lead may each be electroplated. The first die flag and the second die flag may be electrically isolated from the first lead and the second lead.
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
11.
MULTIPLE SUBSTRATE PACKAGE SYSTEMS AND RELATED METHODS
Implementations of a semiconductor package may include a first substrate including a first group of leads physically coupled thereto and a second group of leads physically coupled thereto; a second substrate coupled over the first substrate and physically coupled to the first group of leads and the second group of leads; and one or more semiconductor die coupled between the first substrate and the second substrate. The second group of leads may be electrically isolated from the first substrate.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/24 - Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel, at the normal operating temperature of the device
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
12.
WIRE-IN-DAM PACKAGES AND RELATED SYSTEMS AND METHODS
An electromagnetic irradiation system may include a bulb assembly and a light emitting diode panel. The bulb assembly and light emitting diode panel may be coupled over a package tray conveyor and the bulb assembly and the light emitting diode panel may be configured so that a package tray including a plurality of image sensor packages encounters irradiation from the light emitting diode panel prior to encountering irradiation from the bulb assembly.
A static charge handling system may include an array of photodiodes, a metal grid coupled to the array of photodiodes, and a set of metal projections extending away from the metal grid. The set of metal projections may be configured to direct charge from one of electrostatic discharge or static charge into the metal grid.
A semiconductor device includes a substrate, a first semiconductor region of a first conductivity type over the substrate and a second semiconductor region of the first conductivity type over the first semiconductor region. A trench gate structure includes a trench in the second semiconductor region, a gate conductor, and a gate dielectric separating the gate conductor from the second semiconductor region. A first doped region of a second conductivity type is in the first semiconductor region, wherein the first doped region and the first semiconductor region provide a first charge-balance region. A second doped region of the second conductivity type is in the second semiconductor region and interposed between the trench gate structure and the first doped region, wherein the second doped region and the second semiconductor region provide a second charge-balance region. The second doped region is self-aligned with the trench gate structure.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
A transceiver circuit that includes circuits for cleaning oxidation from input and output pins is disclosed. During a first phase of a cleaning operation, a first cleaner circuit may maintain floating input pins at a voltage level less than a cleaning voltage that is greater than an operating supply voltage. During a second phase of the cleaning operation, the first cleaner circuit may couple the input pins to a ground supply node. A second cleaner circuit may, during the first phase of the cleaning operation, couple the output pins to the cleaning voltage. During the second phase of the cleaning operation, the second cleaner circuit may source respective currents to the output pins.
H01R 43/00 - Apparatus or processes specially adapted for manufacturing, assembling, maintaining, or repairing of line connectors or current collectors or for joining electric conductors
B08B 13/00 - Accessories or details of general applicability for machines or apparatus for cleaning
16.
PACKAGE TRAYS FOR SEMICONDUCTOR PACKAGES AND RELATED METHODS
Implementations of a package tray may include a base and a grid of electromagnetic radiation reflectors coupled to a largest planar side of the base; wherein sidewalls of the grid of electromagnetic radiation reflectors may be configured to direct electromagnetic radiation toward sides of a plurality of semiconductor packages located within the grid. The electromagnetic radiation may be configured to assist in curing a component of the plurality of semiconductor packages.
H01L 21/673 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components using specially adapted carriers
illustrative vehicles, systems, and methods adapt ultrasonic sensing arrays for close-range communication with, e.g., smart devices, parking infrastructure, and other vehicles. As one example, an illustrative vehicle includes: one or more ultrasonic sensors configured for proximity sensing; and a controller configured to use the one or more ultrasonic sensors to receive an acoustic signal from a smart device. As another example, an illustrative vehicle includes one or more microphones configured for at least one of noise cancellation, voice control, emergency vehicle detection, and proximity sensing; and a controller configured to use the one or more microphones to receive an acoustic signal from a smart device, the acoustic signal being in the frequency range between 18 kHz and 25 kHz, inclusive.
G01S 15/931 - Sonar systems specially adapted for specific applications for anti-collision purposes of land vehicles
H04B 11/00 - Transmission systems employing ultrasonic, sonic or infrasonic waves
H04R 1/40 - Arrangements for obtaining desired frequency or directional characteristics for obtaining desired directional characteristic only by combining a number of identical transducers
In a general aspect, a semiconductor device assembly includes a first substrate including a first dielectric layer, and a first patterned metal layer disposed on a surface of the first dielectric layer. The assembly also includes a pre-molded semiconductor device module having a first side disposed on and electrically coupled with the first patterned metal layer, and a second substrate including a second dielectric layer, a second patterned metal layer disposed on a first surface of the second dielectric layer. The second patterned metal layer being is disposed on and electrically coupled with a second side of the module opposite the first side. The second substrate also includes a conductive via defined through the second dielectric layer. The conductive via electrically couples a signal terminal of the module with a patterned metal layer disposed on a second surface of the second dielectric layer opposite the first surface.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/373 - Cooling facilitated by selection of materials for the device
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
A power module includes a substrate, a plurality of semiconductor dies coupled to the substrate, and a clip substrate member having a first surface and a second surface. The first surface is coupled to the plurality of semiconductor dies. The clip substrate member includes a first conductive clip, and a second conductive clip, and a dielectric material portion disposed between the first conductive clip and the second conductive clip. The second surface includes a first contact region and a second contact region. The first contact region includes a portion of the first conductive clip. The second contact region includes a portion of the second conductive clip.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
20.
HIDDEN ULTRASONIC SENSING SYSTEMS SUITABLE FOR ADVANCED DRIVER ASSISTANCE
Illustrative sensor controllers, sensors, sensing systems, and sensing methods, may enable cost-efficient implementation of ADAS (advanced driver-assistance system) features with hidden sensors. As one example, an illustrative sensing method includes: transmitting an acoustic burst through a surface over an ultrasonic transducer; receiving an acoustic signal with a MEMS (micro-electromechanical systems) microphone, the MEMS microphone representing the acoustic signal as an electrical receive signal; and processing the electrical receive signal to detect a reflection of the acoustic burst.
An obstacle monitoring system includes a transducer that receives an ultrasonic echo from an obstacle and generates a signal based on the echo. The system further includes a controller coupled to the transducer that is calibrated based on a frequency response of the transducer and a coupling circuit. The system further includes circuitry generating a damping current, controlled by the controller, that reduces or eliminates reverberation of the transducer.
G10K 11/178 - Methods or devices for protecting against, or for damping, noise or other acoustic waves in general using interference effectsMasking sound by electro-acoustically regenerating the original acoustic waves in anti-phase
22.
LEADFRAME-LESS SEMICONDUCTOR DEVICE ASSEMBLIES WITH DUAL-SIDED COOLING
In a general aspect, a semiconductor device assembly (200) includes a first substrate (220) and a second substrate (210). Patterned metal layers (224, 214) respectively included with the first and second substrates are electrically coupled, respectively, with opposite sides of a pre-molded semiconductor device module (230a). A conductive via (216) is defined through the second substrate. The conductive via electrically couples a signal terminal of the module with another patterned metal layer (217) disposed on a surface of the second substrate opposite the first patterned metal layer.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H01L 25/11 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in subclass
23.
THERMAL PERFORMANCE IMPROVEMENT AND STRESS REDUCTION IN SEMICONDUCTOR DEVICE MODULES
In a general aspect, a method of producing a signal distribution assembly includes forming a first metal layer having a first, planar side and a second, non-planar side opposite the first side. The second side includes a first base portion, a first post extending from the first base portion; and a second post extending from the first base portion. The method also includes molding the first metal layer such that a molding compound is disposed on the second side of the first metal layer with respective upper surfaces of the first and second posts being exposed through the molding compound. The method further includes coupling the first side of the first metal layer to a first surface of a thermally conductive insulator layer and coupling a second metal layer with a second surface of the thermally conductive insulator layer opposite the first surface of the thermally conductive insulator layer.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/373 - Cooling facilitated by selection of materials for the device
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
In a general aspect, a circuit includes a metal-oxide semiconductor field-effect transistor (MOSFET) having a gate, a source, and a drain. The MOSFET has a first breakdown voltage. The circuit also includes a clamping circuit coupled between the drain and the source. The clamping circuit including a diode having a second breakdown voltage that is less than the first breakdown voltage. A cathode of the diode is coupled with the drain of the MOSFET. The clamping circuit further includes an inductor having a first terminal coupled with an anode of the diode, and a second terminal coupled with the source of the MOSFET.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
25.
BUILT-IN SELF TEST WITH CURRENT MEASUREMENT FOR ANALOG CIRCUIT VERIFICATION
Illustrative integrated circuit devices are provided with built-in self test circuit designs and verification methods. One disclosed integrated circuit device includes: an analog circuit block configured to be powered by a current flow from a first power rail and an intermediate node; a current sensor configured to provide digital measurements of the current flow; a built-in self test circuit configured to set the analog circuit block in a sequence of operating modes and coupled to the current sensor to capture for each operating mode a corresponding one of the digital measurements.
A reference buffer circuit for buffering a reference voltage is disclosed. The reference buffer circuit includes an input circuit that may generate a replica of the reference voltage. A feedback circuit may generate a charging current using a current mirror circuit and a bias current. A value of the charging current may be greater than a value of the bias current. The feedback circuit may provide a buffered version of the reference voltage at a reference node using the charging current and the replica voltage. An output stage circuit may sink a compensation current from the reference node.
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
A power system including a gate driver configured with test circuitry to detect faults is disclosed. The power system may be configured to test the fault detection circuitry in order to confirm its ability to detect faults. Various methods and circuit implementations are disclosed to determine the ability of the system to detect faults. The testing may include different configurations and protocols in order to make conclusions about which components are likely responsible for a failure. These components may include components included in the gate driver or externally coupled to the gate driver. The disclose approach does not significantly add complexity because a test input to initiate a test may be communicated from a low voltage side to a high voltage side over a shared communication channel.
H02H 7/20 - Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment
H02H 1/00 - Details of emergency protective circuit arrangements
Illustrative surge protectors and surge protection methods provide accurate clamp level control during voltage transients and surge events. One illustrative surge protector includes: a shunt transistor having a source coupled to ground and a drain coupled to a conductor at a supply voltage; and an operational amplifier having: an output coupled to a gate of the shunt transistor, an inverting input coupled to a reference voltage Vref, and a noninverting input coupled to receive a sense voltage, the sense voltage being a fixed fraction f of the supply voltage, the operational amplifier being configured to drive the shunt transistor to shunt any excess current when the supply voltage reaches a clamp voltage Vc=Vref/f.
A protection circuit is disclosed for use in automotive or industrial high power integrated circuits equipped with reverse battery protection and reverse current protection. The protection circuit prevents formation of parasitic devices that could cause the high power integrated circuit to malfunction or fail to turn on. The protection circuit features asynchronous operation of a pair of MOSFETs coupled between a power supply and a load. The protection circuit can be engaged at start-up or in response to transient conditions associated with a fault.
H02H 3/05 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection Details with means for increasing reliability, e.g. redundancy arrangements
H02H 3/16 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to fault current to earth, frame or mass
H02H 9/00 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
Implementations of an image sensor package may include an optically transmissive cover including a groove along an entire perimeter of the optically transmissive cover; an image sensor die; an adhesive material coupling the optically transmissive cover to the image sensor die; and a mold compound contacting sidewalls of the image sensor die, contacting the adhesive material, and extending into the groove.
Signal converters, systems for power conversion, and methods for adaptive pulse control. The signal converter includes a pulse generator, a level shifter, and a controller. The pulse generator is configured to receive an input control signal for a switch driver. The pulse generator is also configured to generate a set control signal based on the input control signal. The level shifter is configured to generate, based on the set control signal, an output control signal having a first amplitude greater than a second amplitude of the input control signal. The level shifter is also configured to send the output control signal to the switch driver. The controller is configured to detect a common mode transient at a node coupled to the switch driver. The pulse generator is further configured to increase a pulse width of the set control signal when the controller detects the common mode transient.
H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H03K 17/081 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
A receiver coil of an inductive angular position sensor can have circuit features that become smaller than reasonable for high resolution measurement designs. This is especially true when multiple receiver coils are used, such as in a three-phase configuration, and when each of the multiple receiver coils is in a twisted loop configuration. The disclosed inductive angular position sensor utilizes different spatial frequencies for a rotor coil and the receiver coils. For example, the spatial frequency of the receiver coils may be kept smaller than the rotor coil. In this condition, the fundamental frequency of the angular position sensor is shifted to the least common multiple of the spatial frequencies, making the angular resolution of the inductive angular position sensor high, while the circuit features of the receiver coils are maintained at a reasonable size.
G01D 5/20 - Mechanical means for transferring the output of a sensing memberMeans for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for convertingTransducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying inductance, e.g. by a movable armature
A receiver coil of an inductive angular position sensor can have circuit features that become smaller than reasonable for high resolution measurement designs. This is especially true when multiple receiver coils are used, such as in a three-phase configuration, and when each of the multiple receiver coils is in a twisted loop configuration. The disclosed inductive angular position sensor utilizes different spatial frequencies for a rotor coil and the receiver coils. For example, the spatial frequency of the receiver coils may be kept smaller than the rotor coil. In this condition, the fundamental frequency of the angular position sensor is shifted to the least common multiple of the spatial frequencies, making the angular resolution of the inductive angular position sensor high, while the circuit features of the receiver coils are maintained at a reasonable size.
G01D 5/20 - Mechanical means for transferring the output of a sensing memberMeans for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for convertingTransducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying inductance, e.g. by a movable armature
An illustrative controller includes: a transmitter to drive an acoustic transducer to generate a first acoustic burst and a second acoustic burst; a receiver coupled to the acoustic transducer to sense a first response to the first acoustic burst and a second response to the second acoustic burst; and a processing circuit to derive output data from the first and second responses in part by determining an offset frequency difference between the first and second responses, wherein the first acoustic burst has a first characteristic frequency and the second acoustic burst has a second characteristic frequency different from the first characteristic frequency.
A method for attaching a terminal pin to a circuit trace on an electronic substrate. The method includes disposing the electronic substrate on a stage, placing a terminal pin on the circuit trace on the electronic substrate, and directing ultrasound energy generated by a sonotrode to a base region of the terminal pin placed on the circuit trace. The ultrasound energy couples the base region to the circuit trace.
H01R 12/73 - Coupling devices for rigid printing circuits or like structures coupling with the edge of the rigid printed circuits or like structures connecting to other rigid printed circuits or like structures
A dual-side cooling (DSC) semiconductor package includes a first metal-insulator-metal (MIM) substrate having a first insulator layer, first metallic layer, and second metallic layer. A second MIM substrate includes a second insulator layer, third metallic layer, and fourth metallic layer. The third metallic layer includes a first portion having a first contact area and a second portion, electrically isolated from the first portion, having a second contact area. A semiconductor die is coupled with the second metallic layer and is directly coupled with the third metallic layer through one or more solders, sintered layers, electrically conductive tapes, solderable top metal (STM) layers, and/or under bump metal (UBM) layers. The first contact area is electrically coupled with a first electrical contact of the die and the second contact area is electrically coupled with a second electrical contact of the die. The first and fourth metallic layers are exposed through an encapsulant.
An electrical circuit includes positive and negative voltage rails, a reference voltage rail, a non-trimmable bandgap core configured to output a voltage reference on the reference voltage rail, and a trimming element in an auxiliary section located external to the bandgap core. A current source is coupled to the non-trimmable bandgap core and the positive voltage rail. An auxiliary diode arranged in an auxiliary section outside of the bandgap core is coupled to the current source and negative voltage rail. The trimming element is coupled to the current source external to the non-trimmable bandgap core and has an adjustable set point. The adjustable set point is adjusted to inject a corresponding bias current to the auxiliary section during a trimming process and thereby change the voltage reference.
H02M 3/156 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
38.
JET ABLATION DIE SINGULATION SYSTEMS AND RELATED METHODS
Implementations of a method singulating a plurality of semiconductor die. Implementations may include: forming a pattern in a back metal layer coupled on a first side of a semiconductor substrate where the semiconductor substrate includes a plurality of semiconductor die. The method may include etching substantially through a thickness of the semiconductor substrate at the pattern in the back metal layer and jet ablating a layer of passivation material coupled to a second side of the semiconductor substrate to singulate the plurality of semiconductor die.
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
A semiconductor wafer has an edge support ring around a perimeter of the semiconductor wafer and conductive layer formed over a surface of the semiconductor wafer within the edge support ring. A first stencil is disposed over the edge support ring with first openings aligned with the conductive layer. The first stencil includes a horizontal portion over the edge support ring, and a step-down portion extending the first openings to the conductive layer formed over the surface of the semiconductor wafer. The horizontal portion may have a notch with the edge support ring disposed within the notch. A plurality of bumps is dispersed over the first stencil to occupy the first openings over the conductive layer. A second stencil is disposed over the edge support ring with second openings aligned with the conductive layer to deposit a flux material in the second openings over the conductive layer.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
A semiconductor wafer has a base material. The semiconductor wafer may have an edge support ring. A grinding phase of a surface of the semiconductor wafer removes a portion of the base material. The grinder is removed from or lifted off the surface of the semiconductor wafer during a separation phase. The surface of the semiconductor wafer and under the grinder is rinsed during the grinding phase and separation phase to remove particles. A rinsing solution is dispensed from a rinsing solution source to rinse the surface of the semiconductor wafer. The rinsing solution source can move in position while dispensing the rinsing solution to rinse the surface of the semiconductor wafer. The grinding phase and separation phase are repeated during the entire grinding operation, when grinding conductive TSVs, or during the final grinding stages, until the final thickness of the semiconductor wafer is achieved.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
B24B 7/22 - Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfacesAccessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain
B24B 55/06 - Dust extraction equipment on grinding or polishing machines
H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
A method of clamping a voltage includes providing a fin-based field effect transistor (FinFET) device. The FinFET device includes an array of FinFETs. Each FinFET includes a source contact electrically coupled to a fin and a gate contact. The method also includes applying the voltage to the source contact and applying a second voltage to the gate contact. The voltage is greater than the second voltage. The method further includes increasing the voltage to a threshold voltage and conducting current from the source contact to the gate contact in response to the voltage reaching the threshold voltage.
H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
42.
DIAGNOSING POWER RAIL OVER-VOLTAGE AND UNDER-VOLTAGE CONDITIONS
Power monitors, power supply circuits, and methods for operating a power supply. The method includes determining a voltage of a power rail provided to a load device from the power supply. The method also includes detecting that the voltage of the power rail is greater than or equal to an over-voltage threshold. The method further includes incrementing an over-voltage counter when the voltage of the power rail is detected as being greater than or equal to the over-voltage threshold. The method also includes detecting that the over-voltage counter is equal to a threshold value. The method further includes generating an interrupt signal when the over-voltage counter is detected as being equal to the threshold value.
Implementations described herein are related to a semiconductor device package having an improved baseplate. In such an improved baseplate, there is a recess cut out of a region of a surface of the baseplate such that the recess has a first sidewall having a first thickness above a recess base and a second sidewall having a second thickness above the recess base. A substrate, e.g., a direct bonded copper (DBC) substrate, may be attached to the baseplate at a recess base using, e.g., a solder layer between the recess base and a surface of the substrate.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
44.
COPPER PAD METALLIZATION SYSTEMS AND RELATED METHODS
Implementations of a method of forming an interconnect may include forming a seed layer over a plurality of pads; patterning a layer of photoresist with a plurality of openings exposing the plurality of pads; forming a plurality of copper interconnects by electroplating each copper interconnect of the plurality of copper interconnects into each opening of the plurality of openings; removing the layer of photoresist; etching the seed layer; forming one or more layers on the plurality of copper interconnect; and patterning a layer of polyimide over the plurality of copper interconnects to form at least one opening over at least one copper interconnect of the plurality of copper interconnects.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
A system may include an analog-to-digital converter (ADC) that contains a capacitive digital-to-analog converter (CDAC). An input signal for the ADC may be sampled at different times using multi-sampling circuitry. The multi-sampling circuitry may include sampling capacitors that form at least part of the CDAC.
H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
46.
COPPER PAD METALLIZATION SYSTEMS AND RELATED METHODS
Implementations of a method of forming an interconnect may include forming a seed layer (10) over a plurality of pads (6); patterning a layer of photoresist (12) with a plurality of openings (14) exposing the plurality of pads (6); forming a plurality of copper interconnects (18) by electroplating each copper interconnect of the plurality of copper interconnects (18) into each opening of the plurality of openings (14); removing the layer of photoresist (12); etching the seed layer (10); forming one or more layers (24) on the plurality of copper interconnect (18); and patterning a layer of polyimide (26) over the plurality of copper interconnects (18) to form at least one opening (28) over at least one copper interconnect of the plurality of copper interconnects (18).
A multi-phase power system configured to add and remove phases according to a plurality of states can increase the efficiency of the power system, which can increase a battery life in mobile applications. After phases are shed, a load may quickly change requiring all phases to be activated before an over current protection triggers a shutdown. The response of the power system to these load transients may be improved through the use of multiple triggers, which can provide an early warning of the changing load requirements more accurately and consistently than a single trigger.
A multiphase power stage that includes addressing and communication techniques to read temperatures of the phases for thermal load balancing is disclosed. The disclosure describes driver modules that can be assigned addresses for serial communication on a common communication bus by temporarily communicating the addresses over dedicated pulse width modulation connections between the driver modules and the controller. After assignment, a temperature request message, addressed to a driver module, can trigger the driver module to transmit an analog temperature signal to a common temperature bus coupled between the driver modules and the controller. The temperatures of the driver modules may be collected in order to activate and deactivate driver modules based on their temperatures, which can balance a thermal load on the multiphase power stage.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 1/32 - Means for protecting converters other than by automatic disconnection
Secure serial bus communication methods and devices suitable for automotive applications. An illustrative integrated circuit includes: a scrambler configured to process data packets into masked data packets using a configuration or an initial state derived by proprietary processing of a seed value stored in the clear or received via a bus; and a digital-to-analog converter configured to send the masked data packets via the bus.
G06F 21/72 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
A junction field effect transistor (JFET) includes a drift region disposed on a substrate that includes a drain region of the JFET. A lower gate region is disposed on the drift region, a source region is disposed above the lower gate region, and an upper gate region at least partially surrounding the source region and extending laterally beyond the lower gate region is disposed above the source region. The upper gate region extends laterally beyond the lower gate region by a distance defining a gate offset width between the upper gate region and the lower gate region.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
51.
INTEGRATION OF SEMICONDUCTOR DEVICE ASSEMBLIES WITH THERMAL DISSIPATION MECHANISMS
In a general aspect, a semiconductor device assembly includes a metallic chamber configured to transfer thermal energy from a first surface of the metallic chamber to a second surface of the metallic chamber opposite the first surface, a thermally conductive polymer layer disposed on the first surface of the metallic chamber, a patterned metal layer disposed on the thermally conductive polymer layer, and at least one semiconductor die disposed on the patterned metal layer.
A junction field effect transistor (JFET) (100) includes a drift region (110) disposed on a substrate (111) that includes a drain region of the JFET. A lower gate region (106) is disposed on the drift region, a source region (102) is disposed above the lower gate region, and an upper gate region (104) at least partially surrounding the source region and extending laterally beyond the lower gate region is disposed above the source region. The upper gate region extends laterally beyond the lower gate region by a distance defining a gate offset width (Gos) between the upper gate region and the lower gate region.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 21/337 - Field-effect transistors with a PN junction gate
H01L 29/808 - Field-effect transistors with field effect produced by a PN or other rectifying junction gate with a PN junction gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
Implementations of a method of forming a copper feature may include providing a copper layer with a thickness thicker than 1 mm; cutting a trench partially through the thickness leaving a remaining thickness using a laser; and, after cutting, removing the remaining thickness using a water jet.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/373 - Cooling facilitated by selection of materials for the device
A semiconductor device includes an active device region and a plurality of guard rings arranged in a first concentric pattern surrounding the active device region. The semiconductor device also includes a plurality of junctions arranged in a second concentric pattern surrounding the active device region. At least one of the plurality of junctions is arranged between two adjacent guard rings of the plurality of guard rings, and the plurality of junctions have a different resistivity than the plurality of guard rings. The semiconductor device further includes a plurality of coupling paths. At least one of the plurality of coupling paths is arranged to connect two adjacent guard rings of the plurality of guard rings.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 21/266 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation using masks
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
55.
METHODS FOR MITIGATING LAG IN IMAGE SENSOR DEVICES
Implementations of a method of mitigating lag for an image sensor device may include reading a row of data from an Nth frame of image data from an image sensor device; correcting the row of data using truncated row data from an N-1th frame stored in a memory operatively coupled with the image sensor device to form a lag corrected row of data; outputting the lag corrected row of data; truncating the row of data to form truncated row data from the Nth frame; and storing the truncated row data from the Nth frame in the memory.
H04N 25/40 - Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
A compact power inverter is efficiently laid out on a multi-layer direct bond metal (DBM) structure, having a reduced footprint and straight, short-run wire bonds. The compact layout reduces an amount of material needed to fabricate a multi-layer DBM that includes a silicon nitride ceramic layer. The layout is further designed so that wire bonds can be routed without bending around corners. The compact DBM structure and short wire bonds provide a solution that is both low-cost and highly reliable.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
Implementations of a substrate carrier may include a frame including an inner perimeter, the inner perimeter configured to be smaller than a perimeter of an organic substrate panel including multiple semiconductor die coupled thereto; and an outer perimeter configured to be larger than the perimeter of the organic substrate panel; wherein an edge of the frame between the inner perimeter and outer perimeter may be configured to rest against the organic substrate panel to prevent warpage during a heating operation.
H01L 21/673 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components using specially adapted carriers
B65D 61/00 - External frames or supports adapted to be assembled around, or applied to, articles
A compact power inverter (100, 400, 450) is efficiently laid out on a multi-layer direct bond metal (DBM) structure (102), having a reduced footprint and straight, short-run wire bonds (107, 407, 457). The compact layout reduces an amount of material needed to fabricate a multi-layer DBM (102) that includes a silicon nitride ceramic layer (102b, 402b). The layout is further designed so that wire bonds (107, 407, 457) can be routed without bending around corners. The compact DBM structure (102) and short wire bonds (107, 407, 457) provide a solution that is both low-cost and highly reliable.
Implementations of a leadframe for a semiconductor package may include a half-etched gate lead directly coupled to a gate tie bar; a half-etched source lead directly coupled to a source tie bar; and a die flag directly coupled to at least two die flag tie bars. The gate tie bar and the source tie bar may be configured to enable electroplating of a flank of the half-etched gate lead and the half-etched source lead.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
60.
SEMICONDUCTOR PACKAGES WITH WETTABLE FLANKS AND RELATED METHODS
Implementations of a leadframe for a semiconductor package may include a half-etched gate lead directly coupled to a gate tie bar; a half-etched source lead directly coupled to a source tie bar; and a die flag directly coupled to at least two die flag tie bars. The gate tie bar and the source tie bar may be configured to enable electroplating of a flank of the half-etched gate lead and the half-etched source lead.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
61.
METHOD FOR DEFINING A GAP HEIGHT WITHIN AN IMAGE SENSOR PACKAGE
According to an aspect, an image sensor package includes a substrate, an image sensor die coupled to the substrate, a light transmitting member, and a plurality of pillar members disposed between and contacting the image sensor die and the light transmitting member. A height of the plurality of pillar members defines a gap height between an active region of the image sensor die and the light transmitting member. The image sensor package including a bonding material that couples the light transmitting member to the image sensor. The bonding material contacts a side of a pillar member, of the plurality of pillar members, that extends between a first end contacting the light transmitting member and a second end contacting the image sensor die.
Implementations of a semiconductor substrate may include a wafer including a first side and a second side; and a support structure coupled to the wafer at a desired location on the first side, the second side, or both the first side and the second side. The support structure may include an organic compound.
H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
H01L 23/32 - Holders for supporting the complete device in operation, i.e. detachable fixtures
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
Implementations of a semiconductor device may include a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The first largest planar surface, the second largest planar surface, and the thickness may be formed by at least two semiconductor die. The warpage of one of the first largest planar surface or the second largest planar surface may be less than 200 microns.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/32 - Holders for supporting the complete device in operation, i.e. detachable fixtures
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
64.
OFFSET CANCEL SYSTEMS AND METHODS FOR RESOLVER-TYPE SENSORS
Implementations of a resolver sensor system may include a signal amplifier portion configured to be coupled to a magnetoresistive sensor coupled with a movable element where the signal amplifier portion configured to receive a sine signal and a cosine signal from the magnetoresistive sensor; and a sensor offset canceling portion coupled with a signal amplifier portion. The sensor offset canceling portion may be configured to generate a direct current offset correction signal to the signal amplifier portion which uses two or more amplifiers included in the signal amplifier portion to receive the sine signal and the cosine signal and to generate corresponding adjusted digital sine and cosine signals. The signal amplifier portion may be configured to provide the adjusted digital sine signal and the adjusted digital cosine signal to one of the servo signal processor or the system controller for use in determining a position of the movable element.
G01D 5/16 - Mechanical means for transferring the output of a sensing memberMeans for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for convertingTransducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying resistance
An inductive position sensor subsystem is disclosed. The inductive position sensor includes a fine rotor located on a first printed circuit board, and a metallic coarse rotor including a metal support to which the first printed circuit board is coupled. The inductive position sensor also includes a fine sensor receiver and a coarse sensor receiver that generate respective pluralities of sensor signals based on the rotation of the fine rotor and the metallic coarse rotor. The fine sensor receiver and the coarse sensor receiver are located on a second printed circuit board separate from the first printed circuit board.
G01D 5/22 - Mechanical means for transferring the output of a sensing memberMeans for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for convertingTransducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying inductance, e.g. by a movable armature differentially influencing two coils
66.
SCINTILLATOR CRYSTAL AND PHOTOMULTIPLIER ASSEMBLIES WITH IMPROVED EMISSION DETECTION
In a general aspect, an apparatus includes a scintillator crystal, and a semiconductor die including a first side and a second side opposite the first side. The semiconductor die includes a photomultiplier array disposed on the first side. The scintillator crystal is disposed on the first side of the semiconductor die. The apparatus also includes a carrier disposed on the second side of the semiconductor die. The photomultiplier array is electrically coupled with the carrier. The apparatus further includes a molding material disposed on a sidewall defined by at least one of the semiconductor die or the carrier. The molding material is configured to protect the photomultiplier array from moisture ingress.
An imaging system may include a silicon photomultiplier with single-photon avalanche diodes (SPADs). The imaging system may be a LIDAR imaging system with LIDAR processing circuitry. To reduce memory requirements in the LIDAR processing circuitry, a dynamic resolution storage scheme may be used. The LIDAR processing circuitry may include autonomous dynamic resolution circuitry that receives input from a time-to-digital converter (TDC). The autonomous dynamic resolution circuitry may include a plurality of memory banks having different resolutions. Based on the magnitude of the input from the TDC, an appropriate memory bank may be selected. In parallel, an address encoder may select a memory bin based on the input from the TDC.
A die-attach process that creates a bond strength sufficient to hold a die to a substrate while it is handled before being permanently attached is disclosed. The die-attach process includes forming locking features in a metal layer of a substrate so a bond at the die-substrate interface is strengthened. The locking features may include a plurality of cavities or slots formed in a metal layer of the substrate. The cavities and slots can increase a surface area and provide anchor points for a die-attach film placed between the die and the substrate.
Implementations of a pad for an image sensor may include a pad base coupled in a pad opening formed in an image sensor die and a layer of metal directly coupled to the pad base extending to a top surface of the pad opening. The pad base may directly couple with a first metallization layer of the image sensor die.
In a general aspect, an electroplating system (100) includes a vessel (105), an electrolytic plating solution (110) in the vessel, a cathode terminal (120), a first anode terminal (130) and a second (140) anode terminals, a first variable power supply (135), and a second variable power supply (145). The cathode terminal is configured to electrically connect with a workpiece (125) that is submerged in the electrolytic plating solution. The first anode terminal is in the electrolytic plating solution on a first side of the workpiece. The second anode terminal is in the electrolytic plating solution on a second side of the workpiece opposite the first side. The first variable power supply coupled between the cathode terminal and the first anode terminal. The second variable power supply coupled between the cathode terminal and the second anode terminal.
Devices and methods are disclosed for high power inverter modules (100) with enhanced thermal and mechanical performance, for use in electric vehicles. The disclosed devices feature enlarged clips (108) that cover an entire die (104), to distribute mechanical forces, thus preventing die cracks for improved reliability. In these power modules, semiconductor dies (104) are sandwiched between a three-layer direct bond metal (DBM) structure (102) and the enlarged clip. A pre-molded clip assembly (105) can be used that includes integrated metalliization (107) to eliminate the need for external wire bonds. Alternatively, semiconductor dies (104) can be inverted in a flip-chip configuration (701) to face a modified DBM structure (702) that integrates the metallization (707). Simulations of the disclosed power inverters indicate improved efficiency in dissipating heat.
An ignition system may include an igniter circuit to control the current in a coil supplied by a battery based on an input signal from an engine control unit. To prevent overheating, the igniter circuit may be configured to shut down the current in the coil when the input signal is held high for an over dwell period. The disclosed igniter circuit is configured with circuitry to automatically adjust the over dwell period used based on a condition of the battery to prevent overheating without prematurely shutting down. The automatic adjustment includes indirectly monitoring the battery condition based on a current or a voltage of a switching device coupled to the coil.
Implementations of an object file for modeling using a three dimensional modeling module may include a first object defined as a root object, the first object corresponding with a first component of a semiconductor package; a second object corresponding with a second component of the semiconductor package directly physically coupled to the first component of the semiconductor package, the second object including a reference to the root object; and at least a third object corresponding with a third component of the semiconductor package, the third object including a reference to the root object, the third component of the semiconductor package directly coupled with a fourth component of the semiconductor package indirectly physically coupled to the second component of the semiconductor package.
Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side. A first side of an optically transmissive lid may be coupled to the second side of the semiconductor die through one or more dams. The packages may also include a light block material around the semiconductor package extending from the first side of the semiconductor die to a second side of the optically transmissive lid. The package may include an opening in the light block material on the second side of the optically transmissive lid that substantially corresponds with an active area of the semiconductor die.
Implementations of an object file for modeling using a three dimensional modeling module may include a first object defined as a root object, the first object corresponding with a first component of a semiconductor package; a second object corresponding with a second component of the semiconductor package directly physically coupled to the first component of the semiconductor package, the second object including a reference to the root object; and at least a third object corresponding with a third component of the semiconductor package, the third object including a reference to the root object, the third component of the semiconductor package directly coupled with a fourth component of the semiconductor package indirectly physically coupled to the second component of the semiconductor package.
A semiconductor device package may include a leadframe having a first portion with first extended portions and a second portion with second extended portions. Mold material may encapsulate a portion of the leadframe and a portion of a semiconductor die mounted to the leadframe. A first set of contacts of the semiconductor die may be connected to a first surface of the first extended portions, while a second set of contacts may be connected to a first surface of the second extended portions. A mold-locking cavity having the mold material included therein may be disposed in contact with a second surface of the first extended portions opposed to the first surface of the first extended portions, a second surface of the second extended portions opposed to the first surface of the second extended portions, the first portion of the leadframe, and the second portion of the leadframe.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/482 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body
H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
A system may include a hybrid analog-to-digital converter (ADC) that forms a flash ADC in a first mode and a delta-sigma ADC is a second mode. The flash ADC may provide output resulting from a coarse analog-to-digital conversion. The output from the coarse analog-to-digital conversion may be used to configure the delta-sigma ADC to perform a fine analog-to-digital conversion.
A switching regulator is disclosed that includes a driver having a driver-wake circuit configured to report its readiness for operation during a startup period. The driver-wake circuit can operate during startup by temporarily drawing power from the controller's power supply until the driver's power supply has reached a level sufficient to power the driver-wake circuit. The driver-wake circuit is configured to communicate the status of the driver's power supply during startup over a pin typically used to communicate temperature. Thus, the disclosed driver can communicate status during startup without needing extra pins, and because the circuitry is automatically disconnected after startup, very little additional power is consumed.
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
H02M 1/32 - Means for protecting converters other than by automatic disconnection
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
Shielded gate semiconductor devices are disclosed for use in high power applications such as electric vehicles and industrial applications. The devices are formed as mesa (106)/trench (400) structures in which shielded gate electrodes are formed in the trenches. Various trench structures (400, 500, 600, 700) are presented that include tapered portions (401) and end tabs (502, 602, 702, 802) that can be beneficial in managing the distribution of electric charge and associated electric fields. The tapered trenches (400) can be used to increase and stabilize breakdown voltages in a termination region (104) of a semiconductor die (100).
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
Described implementations provide wireless, surface mounting of at least two semiconductor devices on opposed surfaces of a leadframe, to provide an isolated, three-dimensional (3D) configuration. The described implementations minimize electrical failures, even for very high voltage applications, while enabling low inductance and high current. Resulting semiconductor device packages have mounting surfaces that provide desired levels of isolation and insulation, while still enabling straightforward mounting techniques, such as soldering, as well as high levels of thermal reliability.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
A method of detecting zero crossings in an AC input voltage at an input of a power converter, including measuring, at a first time, a first voltage. If the first voltage is positive, the method may include determining that the first time corresponds to a positive half-cycle of the AC input voltage. If the first voltage is equal to approximately zero: a) determining that the first time corresponds to a negative half-cycle of the AC input voltage; b) turning on a high-side switch of the power converter for a first time period; and c) measuring, during the first time period, a second voltage. If the second voltage is less than a first threshold, turning off the high-side switch and repeating b) and c) after a time delay. If the second voltage is less than a second threshold, maintaining the high-side switch in an ON state for a second time period.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 1/32 - Means for protecting converters other than by automatic disconnection
H02M 1/42 - Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
H02M 7/219 - Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration
82.
POWER MODULE PACKAGE WITH MOLDED VIA AND DUAL SIDE PRESS-FIT PIN
A module includes an assembly of a semiconductor device die coupled to a lead frame. A board is disposed below the lead frame. The board includes a plated-through hole (PTH) aligned with an opening in the lead frame above the board. The module further includes a mold body encapsulating at least a portion of the assembly. The mold body includes a through-mold via (TMV) aligned with the opening in the lead frame and with the PTH. The PTH is physically accessible from outside the mold body through the TMV and the opening in the lead frame.
According to an aspect, an image sensor package includes a substrate, an image sensor die coupled to the substrate, and a transparent member including a first surface and a second surface, where the second surface of the transparent member is coupled to the image sensor die via one or more dam members such that an empty space exists between an active area of the image sensor die and the second surface of the transparent member. The image sensor package includes a light blocking member coupled to or defined by the transparent member.
A controller for a power converter for providing an output voltage across a load by modulating a current through an inductive element includes a pulse width modulator stage, a droop signal generation circuit, and a first summing device. The pulse width modulator stage is configured to modulate current into the inductive element in response to an error signal. The droop signal generation circuit is configured to form an alternating current (AC) droop signal in response to controlling a current feedback signal indicative of a current through the inductive element, and to provide a droop signal in response to the AC droop signal. The first summing device is configured to provide the error signal in response to a difference between a sum of a voltage feedback signal and the droop signal, and a reference voltage.
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
85.
PACKAGE COMPRISING A DIRECT BONDED METAL SUBSTRATE AND A COOLING JACKET, METHOD OF FORMING THE PACKAGE AND A DIRECT BONDED METAL SUBSTRATE
A package includes a semiconductor die (15) disposed on a three-layer substrate (100). The three-layer substrate includes a ceramic layer (100-2) disposed between a top metal layer (100-2) and a bottom metal layer (10-3). The semiconductor die is disposed on the top metal layer. An array of mesas (10, 12) is defined in the bottom metal layer with grooves (11) between the mesas forming a path (P) for cooling fluid flow across a surface of the bottom metal layer.
H01L 23/373 - Cooling facilitated by selection of materials for the device
C04B 37/00 - Joining burned ceramic articles with other burned ceramic articles or other articles by heating
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/473 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing liquids
H01L 23/433 - Auxiliary members characterised by their shape, e.g. pistons
Implementations of a method of electroless deposition may include providing a semiconductor substrate including a first largest planar surface and a second largest planar surface; forming a backmetal layer on the second largest planar surface; attaching a tape over the backmetal layer; and electroless depositing a metal layer on a pad included on the first largest planar surface. The method may include, after electroless depositing, removing the tape; and after removing the tape, baking the semiconductor substrate.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
87.
POWER MODULE PACKAGE WITH MOLDED VIA AND DUAL SIDE PRESS-FIT PIN
A module (100, 700) includes an assembly of a semiconductor device die (110) coupled to a lead frame (120, 130, 720, 730). A board (150) is disposed below the lead frame. The board includes a plated-through hole (PTH) (162, 762) aligned with an opening (132, 732) in (the lead frame above the board. The module further includes a mold body (150) encapsulating at least a portion of the assembly. The mold body (150) includes a through-mold via (TMV) (160, 760-1, 760-2) aligned with the opening in the lead frame and with the PTH (162, 732). The PTH is physically accessible from outside the mold body through the TMV (160, 760-1, 760-2) and the opening in the lead frame.
Switching power converters, and methods and primary-side controllers for controlling same. One example is a method of controlling a switching power converter, the method comprising: asserting drive signals applied to a primary switch during a plurality of switching periods; during a first switching period, controlling assertion of a first drive signal based on a sample held by a first capacitor, sampling instantaneous output voltage with a second capacitor, and pre-charging a third capacitor; during a second switching period, controlling assertion of a second drive signal based on a sample held by the second capacitor, sampling instantaneous output voltage with the third capacitor, and pre-charging the first capacitor; and during a third switching period, controlling assertion of a third drive signal based on a sample held by the third capacitor, sampling instantaneous output voltage with the first capacitor, and pre-charging the second capacitor.
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
Implementations of a method of increasing the adhesion of a tape. Implementations may include: mounting a tape to a frame, mounting a substrate to the tape, heating the tape after mounting the substrate at one or more temperatures for a predetermined period of time, and increasing an adhesion of the tape to the substrate through heating the tape.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
An image sensor may perform hybrid pixel binning. In pixel binning, pixel values from multiple pixels are combined into a single representative binning value. In a hybrid pixel binning scheme, different pixel groups may be binned in different ways in a single image sensor. When the range of values in a pixel group is low (indicating a flat surface), a mean or median binning scheme may be used. When the range of values in a pixel group is high (indicating an edge), a spatial weighting binning scheme may be used. When a pixel group has an intermediate range, a blend of the median/mean and spatial weighting may be used to avoid undesired blinking in the binning output. The hybrid binning scheme may reduce noise while still preserving high-frequency detail.
A package includes a semiconductor die disposed on a three-layer substrate. The three-layer substrate includes a ceramic layer disposed between a top metal layer and a bottom metal layer. The semiconductor die is disposed on the top metal layer. An array of mesas is defined in the bottom metal layer with grooves between the mesas forming a path for cooling fluid flow across a surface of the bottom metal layer.
H01L 23/473 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing liquids
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
92.
STRUCTURES AND METHODS FOR SOURCE-DOWN VERTICAL SEMICONDUCTOR DEVICE
A semiconductor device includes a region of semiconductor material having a first side and a second side opposite to the first side. Active device structures are adjacent to the first side, the active device structures comprising source regions and gate electrodes. A first gate conductor is at the first side electrically connected to the gate electrodes, a drain region is at the second side, a second gate conductor is at the second side, and through-semiconductor vias extending from the first side towards the side and electrically connecting the first gate electrode to the second gate electrode. A source electrode is at the first side electrically connected to the source regions, and a drain electrode is at the second side electrically connected to the drain region. The through-semiconductor vias are electrically isolated from the source regions and the drain region. The structure provides a gate/drain up with a source-down configuration.
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
93.
HEMT DEVICES WITH REDUCED SIZE AND HIGH ALIGNMENT TOLERANCE
A High Electron Mobility Transistor (HEMT) includes a source, a drain, a channel layer extending between the source and the drain, a barrier layer formed in contact with the channel layer, and extending between the source and the drain, and a gate formed in contact with, and covering at least a portion of, the barrier layer. The gate has gate edge portions and a gate central portion, and dielectric spacers may be formed over the gate edge portions, with the dielectric spacers having a first width therebetween proximal to the gate, and a second width therebetween distal from the gate, where the second width is longer than the first width.
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
An image sensor may include a pixel array and associated readout paths calibration circuitry. The image sensor may include first column readout circuits formed along a first edge of the pixel array and second column readout circuits formed along a second opposing edge of the pixel array. The readout paths calibration circuitry may include one or more first calibration readout circuits located by the first edge of the array, one or more second calibration readout circuits located by the second edge of the array, and an error detection circuit configured to output an error signal based on signals output from the one or more first calibration readout circuits and the one or more second calibration readout circuits. The one or more second calibration readout circuits and the second column readout circuits can receive a reference voltage that is dynamically adjusted based on the error signal.
An image sensor may include an array of pixels arranged in rows and columns. Each pixel can include a subpixel circuit and one or more subtraction circuits. Each subpixel circuit can be selectively coupled to neighboring subpixel circuits in the same row via horizontal odd and even switches and can be selectively coupled to neighboring subpixel circuits in the same column via vertical odd and even switches. The horizontal and vertical switches can be turned on in separate phases to store difference values from pairs of neighboring subpixels into the one or more subtraction circuits. The difference values can be read out using comparators and one or more shift registers to output an edge image that includes only edge information.
H04N 25/443 - Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by partially reading an SSIS array by reading pixels from selected 2D regions of the array, e.g. for windowing or digital zooming
H04N 25/673 - Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response for non-uniformity detection or correction by using reference sources
In an example, a semiconductor device includes a semiconductor substrate of a first conductivity type and a semiconductor region of the first conductivity type over the semiconductor substrate. A well region of a second conductivity type is in the semiconductor region. A doped region of the first conductivity type is in the well region. A doped region of the second conductivity type is in the well region. A doped region of the second conductivity type is in the semiconductor substrate at a bottom side. A doped region of the first conductivity type is in the semiconductor substrate at the bottom side. A first conductor is at a top side of the semiconductor region and a second conductor is at the bottom side. In some examples, one or more of doped regions at the bottom side is a patterned doped region.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
Implementations of a semiconductor device may include a photodiode included in a second epitaxial layer of a semiconductor substrate; light shield coupled over the photodiode; and a first epitaxial layer located in one or more openings in the light shield. The first epitaxial layer and the second epitaxial layer may form a single crystal.
In some aspects, the techniques described herein relate to an electronic device including: a substrate; a metallization layer, the metallization layer having: a first surface disposed on the substrate; a second surface opposite the first surface; and a corrosion-prevention implant layer disposed in the metallization layer, the corrosion-prevention implant layer extending from the second surface to a depth from the second surface in the metallization layer, the depth being less than a thickness of the metallization layer; and an electrical connector coupled with the second surface.
A semiconductor device component includes a contact pad disposed on a surface of a semiconductor substrate, a seed metal layer disposed on the contact pad, and an interconnect disposed on the seed metal layer. The seed metal layer has a width that is greater than the width of the interconnect with a footer portion of the seed metal layer extending outside the width of the interconnect. The semiconductor device component further includes an etch-resistant protective structure disposed on surfaces of the interconnect and the footer portion of the seed metal layer extending outside the width of the interconnect.
Reset output with open drain configuration for functional safety (FUSA) applications. Example embodiments include methods of operating an output of an integrated circuit (IC) including determining an error condition in the IC; generating a reset signal based on the determining the error condition in the IC; selectively conducting, by a field-effect transistor (FET), a first current between an output terminal and a ground terminal of the IC to drive the output terminal to a low voltage state, and thereby signaling the error condition in the IC; conducting a second current between a signal terminal of the IC and a gate of the FET to drive the FET to a conductive state; and selectively driving, in response to the reset signal, the FET to a non-conductive state.
